[SystemZ] Be more careful about inverting CC masks

System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken.  We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities.  For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2.  If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3.  Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.

Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll.  Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.

The patch also makes it easier to reuse CC results from other instructions.

llvm-svn: 187495

47 files changed, 149 insertions, 124 deletions

diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-03.ll b/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
index 0954f6f4783..846c86fd366 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-03.ll
@@ -9,7 +9,7 @@ define void @f1(i32 %val, i32 *%src) {
 ; CHECK: l %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r0, %r2, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   store atomic i32 %val, i32 *%src seq_cst, align 4
   ret void
diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-04.ll b/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
index d4182783b7d..24615b11565 100644
--- a/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomic-store-04.ll
@@ -9,7 +9,7 @@ define void @f1(i64 %val, i64 *%src) {
 ; CHECK: lg %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r0, %r2, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   store atomic i64 %val, i64 *%src seq_cst, align 8
   ret void
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll
index 2c8598ddd22..25f71f31ef1 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-add-01.ll
@@ -22,7 +22,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll
index 2aff860bd2a..cd4e4784c37 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-add-02.ll
@@ -22,7 +22,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll
index 6a919a724a5..a81af72d1ed 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-add-03.ll
@@ -10,7 +10,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: lr %r0, %r2
 ; CHECK: ar %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -24,7 +24,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 ; CHECK: lr %r0, %r2
 ; CHECK: ahi %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 1 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll
index 3b5c0d0b95f..e7905491f2e 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-add-04.ll
@@ -10,7 +10,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: agr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -24,7 +24,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: aghi %r0, 1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 1 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll
index 5cb5aba7923..6d2f541c3a3 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-and-01.ll
@@ -22,7 +22,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -57,7 +57,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: nilh [[ROT]], 33023
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll
index bc92db141e1..572b22484b2 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-and-02.ll
@@ -22,7 +22,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -57,7 +57,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: nilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll
index 6c7ba23e1b9..8d813a14024 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll
@@ -10,7 +10,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: lr %r0, %r2
 ; CHECK: nr %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -24,7 +24,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 ; CHECK: lr %r0, %r2
 ; CHECK: nilf %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 1 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-and-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-and-04.ll
index 649eeebe5d6..89899a6a03a 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-and-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-and-04.ll
@@ -10,7 +10,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: ngr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -33,7 +33,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: risbg %r0, %r2, 31, 191, 0
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 8589934591 seq_cst
   ret i64 %res
@@ -47,7 +47,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: nihf %r0, 2
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 12884901887 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
index 7368758f612..a15fe573493 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
@@ -24,7 +24,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -97,7 +97,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -134,7 +134,7 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
index e5541b53268..c0ae883202a 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
@@ -24,7 +24,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -97,7 +97,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -134,7 +134,7 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
index 13742b2e419..3a9485af4f6 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
@@ -11,7 +11,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: crjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -26,7 +26,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: crjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw max i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -42,7 +42,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: jle [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umin i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -58,7 +58,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: jhe [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umax i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -166,7 +166,7 @@ define i32 @f13(i32 %dummy, i32 *%ptr) {
 ; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]]
 ; CHECK: lhi [[NEW]], 42
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i32 *%ptr, i32 42 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
index 9efa16b38f7..ebed1475860 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
@@ -11,7 +11,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: cgrjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -26,7 +26,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: cgrjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw max i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -42,7 +42,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: jle [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umin i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -58,7 +58,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: jhe [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umax i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -133,7 +133,7 @@ define i64 @f10(i64 %dummy, i64 *%ptr) {
 ; CHECK: cgrjle %r2, [[LIMIT]], [[KEEP:\..*]]
 ; CHECK: lghi [[NEW]], 42
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i64 *%ptr, i64 42 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
index ec81af21086..db5bb8ff9e7 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
@@ -23,7 +23,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -59,7 +59,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
index 3396f68fa79..6141543e0db 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
@@ -23,7 +23,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -59,7 +59,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
index c511bd608fd..c7a6691083d 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
@@ -11,7 +11,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: nr %r0, %r4
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -26,7 +26,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 ; CHECK: nilf %r0, 1
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i32 *%src, i32 1 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
index cda7aa2673a..91fe639cd72 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
@@ -12,7 +12,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -37,7 +37,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 8589934591 seq_cst
   ret i64 %res
@@ -53,7 +53,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 12884901887 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll
index bf4be43e318..caba621addc 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-or-01.ll
@@ -22,7 +22,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll
index 726d9aaa35c..877c642a35a 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-or-02.ll
@@ -22,7 +22,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll
index 692b11c4cf3..9a0aa86feb5 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll
@@ -10,7 +10,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: lr %r0, %r2
 ; CHECK: or %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -24,7 +24,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 ; CHECK: lr %r0, %r2
 ; CHECK: oill %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 1 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-or-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-or-04.ll
index 47827687659..dbc0f11cc74 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-or-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-or-04.ll
@@ -10,7 +10,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: ogr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -24,7 +24,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: oill %r0, 1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 1 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
index 6d42545631e..2c08ebd9f5f 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
@@ -22,7 +22,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
index 6f8e26e5c08..f82ebd9aaaa 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
@@ -22,7 +22,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
index 64ec603fae8..a3031c6806b 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
@@ -10,7 +10,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: lr %r0, %r2
 ; CHECK: sr %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -24,7 +24,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 ; CHECK: lr %r0, %r2
 ; CHECK: ahi %r0, -1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 1 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
index 18929b8c49d..911648b6137 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
@@ -10,7 +10,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: sgr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -24,7 +24,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 1 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
index 238ce336ac4..52575c63497 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
@@ -20,7 +20,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 24
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
index 635d9d440d2..04be623ada8 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
@@ -20,7 +20,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 16
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
index e5ba4d5900c..a602a02a189 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
@@ -8,7 +8,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r2, %r4, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -114,7 +114,7 @@ define i32 @f10(i32 %dummy, i32 *%src) {
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r2, [[VALUE]], 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i32 *%src, i32 40000 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
index c19b34d9fe0..80c0eeb7121 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
@@ -8,7 +8,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r2, %r4, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -81,7 +81,7 @@ define i64 @f7(i64 %dummy, i64 *%ptr) {
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r2, [[VALUE]], 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i64 *%ptr, i64 3000000000 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
index 969e3ef87c4..e8fef2d31d2 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
@@ -22,7 +22,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
index 10d2e3f592b..9405c2ec0c0 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
@@ -22,7 +22,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
@@ -56,7 +56,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
index 05754e7a0ee..d719d0bd714 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
@@ -10,7 +10,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: lr %r0, %r2
 ; CHECK: xr %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -24,7 +24,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 ; CHECK: lr %r0, %r2
 ; CHECK: xilf %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 1 seq_cst
   ret i32 %res
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
index 1e438bd2dc1..c17a879f37c 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
@@ -10,7 +10,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: xgr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -24,7 +24,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 ; CHECK: lgr %r0, %r2
 ; CHECK: xilf %r0, 1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 1 seq_cst
   ret i64 %res
diff --git a/llvm/test/CodeGen/SystemZ/branch-08.ll b/llvm/test/CodeGen/SystemZ/branch-08.ll
index ee3f5b5f533..c4dc4673dc9 100644
--- a/llvm/test/CodeGen/SystemZ/branch-08.ll
+++ b/llvm/test/CodeGen/SystemZ/branch-08.ll
@@ -9,7 +9,7 @@ declare void @foo() noreturn
 define i32 @f1(i32 %a, i32 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: clr %r2, %r3
-; CHECK: jnhe .L[[LABEL:.*]]
+; CHECK: jl .L[[LABEL:.*]]
 ; CHECK: br %r14
 ; CHECK: .L[[LABEL]]:
 ; CHECK: brasl %r14, foo@PLT
@@ -28,7 +28,7 @@ return:
 ; Same again with a fused compare and branch.
 define i32 @f2(i32 %a) {
 ; CHECK-LABEL: f2:
-; CHECK: cijnlh %r2, 0, .L[[LABEL:.*]]
+; CHECK: cije %r2, 0, .L[[LABEL:.*]]
 ; CHECK: br %r14
 ; CHECK: .L[[LABEL]]:
 ; CHECK: brasl %r14, foo@PLT
diff --git a/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll b/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
index 467fe68be3e..d5ea9778690 100644
--- a/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
@@ -22,7 +22,7 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
-; CHECK-MAIN: jlh [[LOOP]]
+; CHECK-MAIN: jl [[LOOP]]
 ; CHECK-MAIN: [[EXIT]]:
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll b/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
index c7ee898ce27..08c79d717c1 100644
--- a/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
+++ b/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
@@ -22,7 +22,7 @@ define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
-; CHECK-MAIN: jlh [[LOOP]]
+; CHECK-MAIN: jl [[LOOP]]
 ; CHECK-MAIN: [[EXIT]]:
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
diff --git a/llvm/test/CodeGen/SystemZ/cond-move-01.ll b/llvm/test/CodeGen/SystemZ/cond-move-01.ll
index 3ddc820dc1b..088dee0232e 100644
--- a/llvm/test/CodeGen/SystemZ/cond-move-01.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-move-01.ll
@@ -6,7 +6,7 @@
 define i32 @f1(i32 %a, i32 %b, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK: clfi %r4, 42
-; CHECK: locrnl %r2, %r3
+; CHECK: locrhe %r2, %r3
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
   %res = select i1 %cond, i32 %a, i32 %b
@@ -17,9 +17,32 @@ define i32 @f1(i32 %a, i32 %b, i32 %limit) {
 define i64 @f2(i64 %a, i64 %b, i64 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK: clgfi %r4, 42
-; CHECK: locgrnl %r2, %r3
+; CHECK: locgrhe %r2, %r3
 ; CHECK: br %r14
   %cond = icmp ult i64 %limit, 42
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
+
+; Test LOCR in a case that could use COMPARE AND BRANCH.  We prefer using
+; LOCR if possible.
+define i32 @f3(i32 %a, i32 %b, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: chi %r4, 42
+; CHECK: locrlh %r2, %r3
+; CHECK: br %r14
+  %cond = icmp eq i32 %limit, 42
+  %res = select i1 %cond, i32 %a, i32 %b
+  ret i32 %res
+}
+
+; ...and again for LOCGR.
+define i64 @f4(i64 %a, i64 %b, i64 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: cghi %r4, 42
+; CHECK: locgrlh %r2, %r3
+; CHECK: br %r14
+  %cond = icmp eq i64 %limit, 42
+  %res = select i1 %cond, i64 %a, i64 %b
+  ret i64 %res
+}
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-01.ll b/llvm/test/CodeGen/SystemZ/cond-store-01.ll
index a734eeeb410..80e6d916144 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-01.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-01.ll
@@ -24,7 +24,7 @@ define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
 define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -59,7 +59,7 @@ define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
 define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -96,7 +96,7 @@ define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
 define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -133,7 +133,7 @@ define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
 define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -170,7 +170,7 @@ define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
 define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -327,7 +327,7 @@ define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f19:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lb %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: stc %r3, 0(%r2)
@@ -347,6 +347,7 @@ define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
 ; CHECK-LABEL: f20:
 ; CHECK: cs {{%r[0-9]+}},
+; CHECK: jl
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
 ; CHECK: stc {{%r[0-9]+}},
@@ -362,7 +363,7 @@ define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
 define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
 ; CHECK-LABEL: f21:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lb %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: cs {{%r[0-9]+}},
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-02.ll b/llvm/test/CodeGen/SystemZ/cond-store-02.ll
index 58550bf192a..e01a8531bcd 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-02.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-02.ll
@@ -24,7 +24,7 @@ define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
 define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -59,7 +59,7 @@ define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
 define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -96,7 +96,7 @@ define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
 define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -133,7 +133,7 @@ define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
 define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -170,7 +170,7 @@ define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
 define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -327,7 +327,7 @@ define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f19:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lh %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: sth %r3, 0(%r2)
@@ -347,6 +347,7 @@ define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
 ; CHECK-LABEL: f20:
 ; CHECK: cs {{%r[0-9]+}},
+; CHECK: jl
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
 ; CHECK: sth {{%r[0-9]+}},
@@ -362,7 +363,7 @@ define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
 define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
 ; CHECK-LABEL: f21:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lh %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: cs {{%r[0-9]+}},
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-03.ll b/llvm/test/CodeGen/SystemZ/cond-store-03.ll
index e2aeecfd579..e122bc26ac4 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-03.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-03.ll
@@ -24,7 +24,7 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -59,7 +59,7 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
 define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -96,7 +96,7 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
 define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -253,7 +253,7 @@ define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f15:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: l %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: st %r3, 0(%r2)
@@ -288,7 +288,7 @@ define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
 define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
 ; CHECK-LABEL: f17:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: l %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: cs {{%r[0-5]}}, %r3, 0(%r2)
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-04.ll b/llvm/test/CodeGen/SystemZ/cond-store-04.ll
index 1830f27ebdd..4ed23a364ad 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-04.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-04.ll
@@ -24,7 +24,7 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -145,7 +145,7 @@ define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f9:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: stg %r3, 0(%r2)
@@ -180,7 +180,7 @@ define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CSG.
 ; CHECK-LABEL: f11:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: csg {{%r[0-5]}}, %r3, 0(%r2)
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-05.ll b/llvm/test/CodeGen/SystemZ/cond-store-05.ll
index 131d1020cce..e41c8fe4f68 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-05.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-05.ll
@@ -24,7 +24,7 @@ define void @f1(float *%ptr, float %alt, i32 %limit) {
 define void @f2(float *%ptr, float %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -179,7 +179,7 @@ define void @f10(float *%ptr, float %alt, i32 %limit) {
 ; ...likewise stores.  In this case we should have a conditional load into %f0.
 define void @f11(float *%ptr, float %alt, i32 %limit) {
 ; CHECK-LABEL: f11:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: ste %f0, 0(%r2)
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-06.ll b/llvm/test/CodeGen/SystemZ/cond-store-06.ll
index 1c2d716e5ff..759a3e05615 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-06.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-06.ll
@@ -24,7 +24,7 @@ define void @f1(double *%ptr, double %alt, i32 %limit) {
 define void @f2(double *%ptr, double %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -179,7 +179,7 @@ define void @f10(double *%ptr, double %alt, i32 %limit) {
 ; ...likewise stores.  In this case we should have a conditional load into %f0.
 define void @f11(double *%ptr, double %alt, i32 %limit) {
 ; CHECK-LABEL: f11:
-; CHECK: jnl [[LABEL:[^ ]*]]
+; CHECK: jhe [[LABEL:[^ ]*]]
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: std %f0, 0(%r2)
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-07.ll b/llvm/test/CodeGen/SystemZ/cond-store-07.ll
index 291360b96ad..b1df525566a 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-07.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-07.ll
@@ -8,7 +8,7 @@ declare void @foo(i32 *)
 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK: clfi %r4, 42
-; CHECK: stocnl %r3, 0(%r2)
+; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
   %orig = load i32 *%ptr
@@ -35,7 +35,7 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
 define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK: clfi %r4, 42
-; CHECK: stocnl %r3, 0(%r2)
+; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
   %orig = load i32 *%ptr
@@ -66,7 +66,7 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
 define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK: clfi %r4, 42
-; CHECK: stocnl %r3, 0(%r2)
+; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
   %orig = load i32 *%ptr
@@ -96,7 +96,7 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
 define void @f7(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK: clfi %r4, 42
-; CHECK: stocnl %r3, 524284(%r2)
+; CHECK: stoche %r3, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 131071
   %cond = icmp ult i32 %limit, 42
@@ -111,7 +111,7 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: clfi %r4, 42
-; CHECK: stocnl %r3, 0(%r2)
+; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 131072
   %cond = icmp ult i32 %limit, 42
@@ -125,7 +125,7 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) {
 define void @f9(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f9:
 ; CHECK: clfi %r4, 42
-; CHECK: stocnl %r3, -524288(%r2)
+; CHECK: stoche %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 -131072
   %cond = icmp ult i32 %limit, 42
@@ -140,7 +140,7 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524292
 ; CHECK: clfi %r4, 42
-; CHECK: stocnl %r3, 0(%r2)
+; CHECK: stoche %r3, 0(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 -131073
   %cond = icmp ult i32 %limit, 42
@@ -154,7 +154,7 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) {
 define void @f11(i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f11:
 ; CHECK: brasl %r14, foo@PLT
-; CHECK: stocnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: stoche {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: br %r14
   %ptr = alloca i32
diff --git a/llvm/test/CodeGen/SystemZ/cond-store-08.ll b/llvm/test/CodeGen/SystemZ/cond-store-08.ll
index d67281c5afb..56dc7ee7777 100644
--- a/llvm/test/CodeGen/SystemZ/cond-store-08.ll
+++ b/llvm/test/CodeGen/SystemZ/cond-store-08.ll
@@ -8,7 +8,7 @@ declare void @foo(i64 *)
 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK: clfi %r4, 42
-; CHECK: stocgnl %r3, 0(%r2)
+; CHECK: stocghe %r3, 0(%r2)
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 42
   %orig = load i64 *%ptr
@@ -34,7 +34,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK: clfi %r4, 42
-; CHECK: stocgnl %r3, 524280(%r2)
+; CHECK: stocghe %r3, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 65535
   %cond = icmp ult i32 %limit, 42
@@ -49,7 +49,7 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK: agfi %r2, 524288
 ; CHECK: clfi %r4, 42
-; CHECK: stocgnl %r3, 0(%r2)
+; CHECK: stocghe %r3, 0(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 65536
   %cond = icmp ult i32 %limit, 42
@@ -63,7 +63,7 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK: clfi %r4, 42
-; CHECK: stocgnl %r3, -524288(%r2)
+; CHECK: stocghe %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 -65536
   %cond = icmp ult i32 %limit, 42
@@ -78,7 +78,7 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: clfi %r4, 42
-; CHECK: stocgnl %r3, 0(%r2)
+; CHECK: stocghe %r3, 0(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 -65537
   %cond = icmp ult i32 %limit, 42
@@ -92,7 +92,7 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 define void @f7(i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
-; CHECK: stocgnl {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: stocghe {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: br %r14
   %ptr = alloca i64
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-02.ll b/llvm/test/CodeGen/SystemZ/int-cmp-02.ll
index a77711931a0..26e13914349 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-02.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-02.ll
@@ -166,11 +166,11 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 ; critical edge %entry->%while.body, which lost the kills information for CC.
 define void @f12(i32 %a, i32 %b) {
 ; CHECK-LABEL: f12:
-; CHECK: crje %r2,
+; CHECK: cije %r2, 0
 ; CHECK: crjlh %r2,
 ; CHECK: br %r14
 entry:
-  %cmp11 = icmp eq i32 %a, %b
+  %cmp11 = icmp eq i32 %a, 0
   br i1 %cmp11, label %while.end, label %while.body
 
 while.body: