[AVR] Add MIR tests for pseudo instruction expansions

This adds tests for 13 pseudo instruction expansions.

llvm-svn: 289039

13 files changed, 308 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
new file mode 100644
index 00000000000..475d5b39299
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit add with carry pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_adcwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_adcwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_adcwrdrr
+
+    ; CHECK:       %r14 = ADCRdRr %r14, %r20, implicit-def %sreg, implicit %sreg
+    ; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+    %r15r14 = ADCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
new file mode 100644
index 00000000000..5af8db15951
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit ANDO pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_andiwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_andiwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_andiwrdrr
+
+    ; CHECK:      %r20 = ANDIRdK %r20, 175, implicit-def dead %sreg
+    ; CHECK-NEXT: %r21 = ANDIRdK %r21, 250, implicit-def %sreg
+
+    %r21r20 = ANDIWRdK %r17r16, 64175, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
new file mode 100644
index 00000000000..c9458e9ba5d
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit AND pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_andwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_andwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_andwrdrr
+
+    ; CHECK:      %r14 = ANDRdRr %r14, %r20, implicit-def dead %sreg
+    ; CHECK-NEXT: %r15 = ANDRdRr %r15, %r21, implicit-def %sreg
+
+    %r15r14 = ANDWRdRr %r15r14, %r21r20, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
new file mode 100644
index 00000000000..282d601686a
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit COM pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_comwrd() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_comwrd
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_comwrd
+
+    ; CHECK:      %r14 = COMRd %r14, implicit-def dead %sreg
+    ; CHECK-NEXT: %r15 = COMRd %r15, implicit-def %sreg
+
+    %r15r14 = COMWRd %r9r8, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
new file mode 100644
index 00000000000..cbc742964c1
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# XFAIL: *
+
+# This test checks the expansion of the 16-bit CPCW pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_cpcwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_cpcwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_cpcwrdrr
+
+    %r15r14 = CPCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
new file mode 100644
index 00000000000..37630148bd8
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# XFAIL: *
+
+# This test checks the expansion of the 16-bit CPW pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_cpwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_cpwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_cpwrdrr
+
+    %r15r14 = CPWRdRr %r15r14, %r21r20, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
new file mode 100644
index 00000000000..8769c12cbb1
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit EOR pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_eorwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_eorwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_eorwrdrr
+
+    ; CHECK:      %r14 = EORRdRr %r14, %r20, implicit-def dead %sreg
+    ; CHECK-NEXT: %r15 = EORRdRr %r15, %r21, implicit-def %sreg
+
+    %r15r14 = EORWRdRr %r15r14, %r21r20, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
new file mode 100644
index 00000000000..92bc36769eb
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit OR pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_oriwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_oriwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_oriwrdrr
+
+    ; CHECK:      %r20 = ORIRdK %r20, 175, implicit-def dead %sreg
+    ; CHECK-NEXT: %r21 = ORIRdK %r21, 250, implicit-def %sreg
+
+    %r21r20 = ORIWRdK %r17r16, 64175, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
new file mode 100644
index 00000000000..f7a377ec860
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit OR pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_orwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_orwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_orwrdrr
+
+    ; CHECK:      %r14 = ORRdRr %r14, %r20, implicit-def dead %sreg
+    ; CHECK-NEXT: %r15 = ORRdRr %r15, %r21, implicit-def %sreg
+
+    %r15r14 = ORWRdRr %r15r14, %r21r20, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
new file mode 100644
index 00000000000..9152c6d9126
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_sbciwrdk() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_sbciwrdk
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_sbciwrdk
+
+    ; CHECK:      %r20 = SBCIRdK %r20, 175, implicit-def %sreg, implicit killed %sreg
+    ; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
+
+    %r21r20 = SBCIWRdK %r17r16, 64175, implicit-def %sreg, implicit %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
new file mode 100644
index 00000000000..9159906b76a
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_sbcwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_sbcwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_sbcwrdrr
+
+    ; CHECK:      %r14 = SBCRdRr %r14, %r20, implicit-def %sreg
+    ; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+    %r15r14 = SBCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
new file mode 100644
index 00000000000..95c68c0a122
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit subtraction pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_subiwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_subiwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_subiwrdrr
+
+    ; CHECK:      %r20 = SUBIRdK %r20, 175, implicit-def %sreg
+    ; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
+
+    %r21r20 = SUBIWRdK %r17r16, 64175, implicit-def %sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
new file mode 100644
index 00000000000..9892cf5b7f3
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit subtraction pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_subwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_subwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_subwrdrr
+
+    ; CHECK:      %r14 = SUBRdRr %r14, %r20, implicit-def %sreg
+    ; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+    %r15r14 = SUBWRdRr %r15r14, %r21r20, implicit-def %sreg
+...