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| author | Sid Manning <sidneym@codeaurora.org> | 2014-09-25 13:09:54 +0000 |
|---|---|---|
| committer | Sid Manning <sidneym@codeaurora.org> | 2014-09-25 13:09:54 +0000 |
| commit | 31f712556206cdf9ec8e15de11f56b092ac4cdae (patch) | |
| tree | aef94e29547711b30ee11d3cdc7ce762896a4cdc /llvm/test/CodeGen | |
| parent | 621589e7c0c2fcf65cff68a5d667eb1307a2ae5c (diff) | |
| download | bcm5719-llvm-31f712556206cdf9ec8e15de11f56b092ac4cdae.tar.gz bcm5719-llvm-31f712556206cdf9ec8e15de11f56b092ac4cdae.zip | |
Add missing attributes !cmp.[eq,gt,gtu] instructions.
These instructions do not indicate they are extendable or the
number of bits in the extendable operand. Rename to match
architected names. Add a testcase for the intrinsics.
llvm-svn: 218453
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/cmp-not.ll | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/cmp-not.ll b/llvm/test/CodeGen/Hexagon/cmp-not.ll new file mode 100644 index 00000000000..abcddc38b23 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/cmp-not.ll @@ -0,0 +1,50 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate matching compare insn. + +; Function Attrs: nounwind +define i32 @neqi(i32 %argc) #0 { +entry: + %p = alloca i8, align 1 + %0 = tail call i1 @llvm.hexagon.C4.cmpneqi(i32 %argc, i32 512) + %conv = zext i1 %0 to i8 + store volatile i8 %conv, i8* %p, align 1 + %p.0.p.0. = load volatile i8* %p, align 1 + %conv1 = zext i8 %p.0.p.0. to i32 + ret i32 %conv1 +} +; CHECK: p{{[0-3]}}{{ *}} = !cmp.eq(r{{[0-9]+}}, ##512) + +; Function Attrs: nounwind readnone +declare i1 @llvm.hexagon.C4.cmpneqi(i32, i32) #1 + +; Function Attrs: nounwind +define i32 @ngti(i32 %argc) #0 { +entry: + %p = alloca i8, align 1 + %0 = tail call i1 @llvm.hexagon.C4.cmpltei(i32 %argc, i32 4) + %conv = zext i1 %0 to i8 + store volatile i8 %conv, i8* %p, align 1 + %p.0.p.0. = load volatile i8* %p, align 1 + %conv1 = zext i8 %p.0.p.0. to i32 + ret i32 %conv1 +} +; CHECK: p{{[0-3]}}{{ *}} = !cmp.gt(r{{[0-9]+}}, #4) + +; Function Attrs: nounwind readnone +declare i1 @llvm.hexagon.C4.cmpltei(i32, i32) #1 + +; Function Attrs: nounwind +define i32 @ngtui(i32 %argc) #0 { +entry: + %p = alloca i8, align 1 + %0 = tail call i1 @llvm.hexagon.C4.cmplteui(i32 %argc, i32 4) + %conv = zext i1 %0 to i8 + store volatile i8 %conv, i8* %p, align 1 + %p.0.p.0. = load volatile i8* %p, align 1 + %conv1 = zext i8 %p.0.p.0. to i32 + ret i32 %conv1 +} +; CHECK: p{{[0-3]}}{{ *}} = !cmp.gtu(r{{[0-9]+}}, #4) + +; Function Attrs: nounwind readnone +declare i1 @llvm.hexagon.C4.cmplteui(i32, i32) #1 |

