diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2013-04-05 23:31:35 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-04-05 23:31:35 +0000 |
| commit | 2f21c7e551e119de7c428eb649176ad581bfda70 (patch) | |
| tree | 7b630ed93ed8dbe51bb14861eda01b46696a55b6 /llvm/test/CodeGen | |
| parent | edbf1eb42be8108bd4d16674f77a08ea391f06fa (diff) | |
| download | bcm5719-llvm-2f21c7e551e119de7c428eb649176ad581bfda70.tar.gz bcm5719-llvm-2f21c7e551e119de7c428eb649176ad581bfda70.zip | |
R600/SI: Add processor types for each SI variant
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/R600/imm.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/llvm.SI.sample.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/lshl.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/lshr.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/mulhu.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/seto.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/setuo.ll | 2 |
8 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/R600/imm.ll b/llvm/test/CodeGen/R600/imm.ll index b43f91722e2..02b73096ce3 100644 --- a/llvm/test/CodeGen/R600/imm.ll +++ b/llvm/test/CodeGen/R600/imm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ; XXX: Enable once SI supports buffer stores ; XFAIL: * diff --git a/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll index bf0cdaa2fa3..e45722c3fa6 100644 --- a/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll +++ b/llvm/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: S_MOV_B32 ;CHECK-NEXT: V_INTERP_MOV_F32 diff --git a/llvm/test/CodeGen/R600/llvm.SI.sample.ll b/llvm/test/CodeGen/R600/llvm.SI.sample.ll index c724395b98c..5bdb246a37f 100644 --- a/llvm/test/CodeGen/R600/llvm.SI.sample.ll +++ b/llvm/test/CodeGen/R600/llvm.SI.sample.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: IMAGE_SAMPLE ;CHECK: IMAGE_SAMPLE diff --git a/llvm/test/CodeGen/R600/lshl.ll b/llvm/test/CodeGen/R600/lshl.ll index 423adb9da90..fb698da6271 100644 --- a/llvm/test/CodeGen/R600/lshl.ll +++ b/llvm/test/CodeGen/R600/lshl.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0 diff --git a/llvm/test/CodeGen/R600/lshr.ll b/llvm/test/CodeGen/R600/lshr.ll index 551eac1d76b..e0ed3ac0786 100644 --- a/llvm/test/CodeGen/R600/lshr.ll +++ b/llvm/test/CodeGen/R600/lshr.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0 diff --git a/llvm/test/CodeGen/R600/mulhu.ll b/llvm/test/CodeGen/R600/mulhu.ll index 28744e00c3c..bc17a597873 100644 --- a/llvm/test/CodeGen/R600/mulhu.ll +++ b/llvm/test/CodeGen/R600/mulhu.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_MOV_B32_e32 VGPR1, -1431655765 ;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0 diff --git a/llvm/test/CodeGen/R600/seto.ll b/llvm/test/CodeGen/R600/seto.ll index 5ab4b87d570..4622203ffdb 100644 --- a/llvm/test/CodeGen/R600/seto.ll +++ b/llvm/test/CodeGen/R600/seto.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 diff --git a/llvm/test/CodeGen/R600/setuo.ll b/llvm/test/CodeGen/R600/setuo.ll index 320835576d4..0bf5801b1c3 100644 --- a/llvm/test/CodeGen/R600/setuo.ll +++ b/llvm/test/CodeGen/R600/setuo.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 |
