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authorCraig Topper <craig.topper@intel.com>2018-02-16 07:16:15 +0000
committerCraig Topper <craig.topper@intel.com>2018-02-16 07:16:15 +0000
commit2e4b838c06cc6a5f659ec75f79b88bd702a2125f (patch)
treec21b56d30137136d1209d82547a00d4f1e4b80d2 /llvm/test/CodeGen
parent5d9e30104254467f0f4acdaa2b7628ae271883ea (diff)
downloadbcm5719-llvm-2e4b838c06cc6a5f659ec75f79b88bd702a2125f.tar.gz
bcm5719-llvm-2e4b838c06cc6a5f659ec75f79b88bd702a2125f.zip
[X86] Allow CMOVs of constants to be sign extended from i32.
Sign extending i32 constants only requires a REX prefix as does widening the CMOV. This is cheaper than the explicit sign extend op. llvm-svn: 325318
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/cmov-promotion.ll7
-rw-r--r--llvm/test/CodeGen/X86/vector-compare-all_of.ll25
2 files changed, 13 insertions, 19 deletions
diff --git a/llvm/test/CodeGen/X86/cmov-promotion.ll b/llvm/test/CodeGen/X86/cmov-promotion.ll
index 9dc137aab28..59ddc77b9c7 100644
--- a/llvm/test/CodeGen/X86/cmov-promotion.ll
+++ b/llvm/test/CodeGen/X86/cmov-promotion.ll
@@ -294,10 +294,9 @@ define i64 @cmov_spromotion_32_to_64(i1 %c) {
; CMOV-LABEL: cmov_spromotion_32_to_64:
; CMOV: # %bb.0:
; CMOV-NEXT: testb $1, %dil
-; CMOV-NEXT: movl $12414, %eax # imm = 0x307E
-; CMOV-NEXT: movl $-1, %ecx
-; CMOV-NEXT: cmovnel %eax, %ecx
-; CMOV-NEXT: movslq %ecx, %rax
+; CMOV-NEXT: movl $12414, %ecx # imm = 0x307E
+; CMOV-NEXT: movq $-1, %rax
+; CMOV-NEXT: cmovneq %rcx, %rax
; CMOV-NEXT: retq
;
; NO_CMOV-LABEL: cmov_spromotion_32_to_64:
diff --git a/llvm/test/CodeGen/X86/vector-compare-all_of.ll b/llvm/test/CodeGen/X86/vector-compare-all_of.ll
index 0a756dfc8a4..f419b30e549 100644
--- a/llvm/test/CodeGen/X86/vector-compare-all_of.ll
+++ b/llvm/test/CodeGen/X86/vector-compare-all_of.ll
@@ -87,9 +87,8 @@ define i64 @test_v4f64_legal_sext(<4 x double> %a0, <4 x double> %a1) {
; SSE-NEXT: movmskps %xmm2, %eax
; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: cmpl $15, %eax
-; SSE-NEXT: movl $-1, %eax
-; SSE-NEXT: cmovnel %ecx, %eax
-; SSE-NEXT: cltq
+; SSE-NEXT: movq $-1, %rax
+; SSE-NEXT: cmovneq %rcx, %rax
; SSE-NEXT: retq
;
; AVX-LABEL: test_v4f64_legal_sext:
@@ -100,9 +99,8 @@ define i64 @test_v4f64_legal_sext(<4 x double> %a0, <4 x double> %a1) {
; AVX-NEXT: vmovmskps %xmm0, %eax
; AVX-NEXT: xorl %ecx, %ecx
; AVX-NEXT: cmpl $15, %eax
-; AVX-NEXT: movl $-1, %eax
-; AVX-NEXT: cmovnel %ecx, %eax
-; AVX-NEXT: cltq
+; AVX-NEXT: movq $-1, %rax
+; AVX-NEXT: cmovneq %rcx, %rax
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
;
@@ -369,9 +367,8 @@ define i64 @test_v4i64_legal_sext(<4 x i64> %a0, <4 x i64> %a1) {
; SSE-NEXT: movmskps %xmm0, %eax
; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: cmpl $15, %eax
-; SSE-NEXT: movl $-1, %eax
-; SSE-NEXT: cmovnel %ecx, %eax
-; SSE-NEXT: cltq
+; SSE-NEXT: movq $-1, %rax
+; SSE-NEXT: cmovneq %rcx, %rax
; SSE-NEXT: retq
;
; AVX1-LABEL: test_v4i64_legal_sext:
@@ -384,9 +381,8 @@ define i64 @test_v4i64_legal_sext(<4 x i64> %a0, <4 x i64> %a1) {
; AVX1-NEXT: vmovmskps %xmm0, %eax
; AVX1-NEXT: xorl %ecx, %ecx
; AVX1-NEXT: cmpl $15, %eax
-; AVX1-NEXT: movl $-1, %eax
-; AVX1-NEXT: cmovnel %ecx, %eax
-; AVX1-NEXT: cltq
+; AVX1-NEXT: movq $-1, %rax
+; AVX1-NEXT: cmovneq %rcx, %rax
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
@@ -398,9 +394,8 @@ define i64 @test_v4i64_legal_sext(<4 x i64> %a0, <4 x i64> %a1) {
; AVX2-NEXT: vmovmskps %xmm0, %eax
; AVX2-NEXT: xorl %ecx, %ecx
; AVX2-NEXT: cmpl $15, %eax
-; AVX2-NEXT: movl $-1, %eax
-; AVX2-NEXT: cmovnel %ecx, %eax
-; AVX2-NEXT: cltq
+; AVX2-NEXT: movq $-1, %rax
+; AVX2-NEXT: cmovneq %rcx, %rax
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
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