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| author | Stefan Pintilie <stefanp@ca.ibm.com> | 2018-03-26 17:39:18 +0000 |
|---|---|---|
| committer | Stefan Pintilie <stefanp@ca.ibm.com> | 2018-03-26 17:39:18 +0000 |
| commit | 26d4f923c4bca68cc20fa7c6a7500bb9f4ad8b28 (patch) | |
| tree | 007c99ebc54322d99d27b023d8583b827a2717a3 /llvm/test/CodeGen | |
| parent | 17e4eeaa8bfdd8255a0950c8401e923b577da9cf (diff) | |
| download | bcm5719-llvm-26d4f923c4bca68cc20fa7c6a7500bb9f4ad8b28.tar.gz bcm5719-llvm-26d4f923c4bca68cc20fa7c6a7500bb9f4ad8b28.zip | |
[PowerPC] Infrastructure work. Implement getting the opcode for a spill in one place.
A new function getOpcodeForSpill should now be the only place to get
the opcode for a given spilled register.
Differential Revision: https://reviews.llvm.org/D43086
llvm-svn: 328556
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll b/llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll index 92427f5ccde..17ff21fcafe 100644 --- a/llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll +++ b/llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll @@ -24,14 +24,14 @@ define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: blr ; ; CHECK-PWR9-LABEL: testSpill: -; CHECK-PWR9: stxv 62, 80(1) # 16-byte Folded Spill -; CHECK-PWR9: stxv 63, 96(1) # 16-byte Folded Spill -; CHECK-PWR9: stxv 60, 48(1) # 16-byte Folded Spill -; CHECK-PWR9: stxv 61, 64(1) # 16-byte Folded Spill -; CHECK-PWR9: lxv 63, 96(1) # 16-byte Folded Reload -; CHECK-PWR9: lxv 62, 80(1) # 16-byte Folded Reload -; CHECK-PWR9: lxv 61, 64(1) # 16-byte Folded Reload -; CHECK-PWR9: lxv 60, 48(1) # 16-byte Folded Reload +; CHECK-PWR9: stxv 62, 64(1) # 16-byte Folded Spill +; CHECK-PWR9: stxv 63, 80(1) # 16-byte Folded Spill +; CHECK-PWR9: stxv 60, 32(1) # 16-byte Folded Spill +; CHECK-PWR9: stxv 61, 48(1) # 16-byte Folded Spill +; CHECK-PWR9: lxv 63, 80(1) # 16-byte Folded Reload +; CHECK-PWR9: lxv 62, 64(1) # 16-byte Folded Reload +; CHECK-PWR9: lxv 61, 48(1) # 16-byte Folded Reload +; CHECK-PWR9: lxv 60, 32(1) # 16-byte Folded Reload ; CHECK-PWR9: mtlr 0 ; CHECK-PWR9-NEXT: blr |
