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| author | Bob Wilson <bob.wilson@apple.com> | 2010-07-09 00:38:12 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-07-09 00:38:12 +0000 |
| commit | 21eed476e8479ae1d14e4968c7edd69bb3bbcd04 (patch) | |
| tree | cd9b46b3810a85f8ce64a703df05310323a884b1 /llvm/test/CodeGen | |
| parent | 061d70ad2cf1118ed066da73ff0e933a7afbd37d (diff) | |
| download | bcm5719-llvm-21eed476e8479ae1d14e4968c7edd69bb3bbcd04.tar.gz bcm5719-llvm-21eed476e8479ae1d14e4968c7edd69bb3bbcd04.zip | |
Reenable DAG combining for vector shuffles. It looks like it was temporarily
disabled and then never turned back on again. Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.
llvm-svn: 107941
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll | 21 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/reg_sequence.ll | 1 |
2 files changed, 12 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll b/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll index 389629e5966..bf0bb404172 100644 --- a/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll +++ b/llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll @@ -4,19 +4,22 @@ target triple = "thumbv7-apple-darwin10" ; This tests the fast register allocator's handling of partial redefines: ; -; %reg1026<def> = VMOVv16i8 0, pred:14, pred:%reg0 -; %reg1028:dsub_1<def> = EXTRACT_SUBREG %reg1026<kill>, 1 +; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025... +; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill> ; -; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef, -; it cannot also get %Q0. +; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial +; redef, it cannot also get %Q0. -; CHECK: vmov.i8 q0, #0x0 -; CHECK-NOT: vld1.64 {d0,d1} +; CHECK: vld1.64 {d0, d1}, [r0] +; CHECK-NOT: vld1.64 {d0, d1} ; CHECK: vmov.f64 d3, d0 -define i32 @main(i32 %argc, i8** %argv) nounwind { +define i32 @test(i8* %arg) nounwind { entry: - %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1] - store <2 x i64> %0, <2 x i64>* undef, align 16 + %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg) + %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2> + store <2 x i64> %1, <2 x i64>* undef, align 16 ret i32 undef } + +declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index b00020c3950..1c4552a4884 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -270,7 +270,6 @@ define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: ; CHECK: vmov.i32 q1, #0x3F000000 -; CHECK: vdup.32 q0, d0[0] ; CHECK: vmov d0, d1 ; CHECK: vmla.f32 q0, q0, d0[0] %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] |
