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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-18 19:54:42 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-18 19:54:42 +0000 |
| commit | 203876f104c6f45262c70ddf4c9b77ea2b9523c7 (patch) | |
| tree | 2f674cfe7664bbcc0d672aee47718fa2da11cb08 /llvm/test/CodeGen | |
| parent | c8faf3a93cc154077234c67d9bf2fbc93d120780 (diff) | |
| download | bcm5719-llvm-203876f104c6f45262c70ddf4c9b77ea2b9523c7.tar.gz bcm5719-llvm-203876f104c6f45262c70ddf4c9b77ea2b9523c7.zip | |
[X86][Btver2] Fix crc32 schedule costs
The default is currently FAdd for some reason
llvm-svn: 327807
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/X86/sse42-schedule.ll | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/X86/sse42-schedule.ll b/llvm/test/CodeGen/X86/sse42-schedule.ll index 26c72aaca10..bbf8acc123c 100644 --- a/llvm/test/CodeGen/X86/sse42-schedule.ll +++ b/llvm/test/CodeGen/X86/sse42-schedule.ll @@ -62,8 +62,8 @@ define i32 @crc32_32_8(i32 %a0, i8 %a1, i8 *%a2) { ; ; BTVER2-LABEL: crc32_32_8: ; BTVER2: # %bb.0: -; BTVER2-NEXT: crc32b %sil, %edi # sched: [3:1.00] -; BTVER2-NEXT: crc32b (%rdx), %edi # sched: [8:1.00] +; BTVER2-NEXT: crc32b %sil, %edi # sched: [3:2.00] +; BTVER2-NEXT: crc32b (%rdx), %edi # sched: [6:2.00] ; BTVER2-NEXT: movl %edi, %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; @@ -132,8 +132,8 @@ define i32 @crc32_32_16(i32 %a0, i16 %a1, i16 *%a2) { ; ; BTVER2-LABEL: crc32_32_16: ; BTVER2: # %bb.0: -; BTVER2-NEXT: crc32w %si, %edi # sched: [3:1.00] -; BTVER2-NEXT: crc32w (%rdx), %edi # sched: [8:1.00] +; BTVER2-NEXT: crc32w %si, %edi # sched: [3:2.00] +; BTVER2-NEXT: crc32w (%rdx), %edi # sched: [6:2.00] ; BTVER2-NEXT: movl %edi, %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; @@ -202,8 +202,8 @@ define i32 @crc32_32_32(i32 %a0, i32 %a1, i32 *%a2) { ; ; BTVER2-LABEL: crc32_32_32: ; BTVER2: # %bb.0: -; BTVER2-NEXT: crc32l %esi, %edi # sched: [3:1.00] -; BTVER2-NEXT: crc32l (%rdx), %edi # sched: [8:1.00] +; BTVER2-NEXT: crc32l %esi, %edi # sched: [3:2.00] +; BTVER2-NEXT: crc32l (%rdx), %edi # sched: [6:2.00] ; BTVER2-NEXT: movl %edi, %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; @@ -272,8 +272,8 @@ define i64 @crc32_64_8(i64 %a0, i8 %a1, i8 *%a2) nounwind { ; ; BTVER2-LABEL: crc32_64_8: ; BTVER2: # %bb.0: -; BTVER2-NEXT: crc32b %sil, %edi # sched: [3:1.00] -; BTVER2-NEXT: crc32b (%rdx), %edi # sched: [8:1.00] +; BTVER2-NEXT: crc32b %sil, %edi # sched: [3:2.00] +; BTVER2-NEXT: crc32b (%rdx), %edi # sched: [6:2.00] ; BTVER2-NEXT: movq %rdi, %rax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; @@ -342,8 +342,8 @@ define i64 @crc32_64_64(i64 %a0, i64 %a1, i64 *%a2) { ; ; BTVER2-LABEL: crc32_64_64: ; BTVER2: # %bb.0: -; BTVER2-NEXT: crc32q %rsi, %rdi # sched: [3:1.00] -; BTVER2-NEXT: crc32q (%rdx), %rdi # sched: [8:1.00] +; BTVER2-NEXT: crc32q %rsi, %rdi # sched: [3:2.00] +; BTVER2-NEXT: crc32q (%rdx), %rdi # sched: [6:2.00] ; BTVER2-NEXT: movq %rdi, %rax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; |
