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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-02-25 21:36:18 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-02-25 21:36:18 +0000 |
| commit | 1f15bff0dfbc704565e5fcfaa3a5336a67bf9705 (patch) | |
| tree | 3a3b3b18339687dc9269c00af195bb4d212659ff /llvm/test/CodeGen | |
| parent | 3b79b2ab4e35353e63ba323a3de4b0a70c61a5f1 (diff) | |
| download | bcm5719-llvm-1f15bff0dfbc704565e5fcfaa3a5336a67bf9705.tar.gz bcm5719-llvm-1f15bff0dfbc704565e5fcfaa3a5336a67bf9705.zip | |
R600/SI: Custom select 64-bit ADD
llvm-svn: 202194
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/R600/add.ll | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/add_i64.ll | 23 |
2 files changed, 27 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/R600/add.ll b/llvm/test/CodeGen/R600/add.ll index e4e7bc6c7f8..8de87f4999f 100644 --- a/llvm/test/CodeGen/R600/add.ll +++ b/llvm/test/CodeGen/R600/add.ll @@ -75,3 +75,13 @@ entry: store <8 x i32> %0, <8 x i32> addrspace(1)* %out ret void } + +; FUNC-LABEL: @add64 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADDC_U32 +define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = add i64 %a, %b + store i64 %0, i64 addrspace(1)* %out + ret void +} diff --git a/llvm/test/CodeGen/R600/add_i64.ll b/llvm/test/CodeGen/R600/add_i64.ll index 303a1cb0391..82cd8a9170d 100644 --- a/llvm/test/CodeGen/R600/add_i64.ll +++ b/llvm/test/CodeGen/R600/add_i64.ll @@ -1,14 +1,13 @@ -; XFAIL: * -; This will fail until i64 add is enabled - ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s -declare i32 @llvm.SI.tid() readnone +declare i32 @llvm.r600.read.tidig.x() readnone ; SI-LABEL: @test_i64_vreg: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) { - %tid = call i32 @llvm.SI.tid() readnone + %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid %a = load i64 addrspace(1)* %a_ptr @@ -20,6 +19,8 @@ define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa ; Check that the SGPR add operand is correctly moved to a VGPR. ; SI-LABEL: @sgpr_operand: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { %foo = load i64 addrspace(1)* %in, align 8 %result = add i64 %foo, %a @@ -31,6 +32,8 @@ define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noal ; SGPR as other operand. ; ; SI-LABEL: @sgpr_operand_reversed: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { %foo = load i64 addrspace(1)* %in, align 8 %result = add i64 %a, %foo @@ -40,6 +43,10 @@ define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace ; SI-LABEL: @test_v2i64_sreg: +; SI: S_ADD_I32 +; SI: S_ADDC_U32 +; SI: S_ADD_I32 +; SI: S_ADDC_U32 define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) { %result = add <2 x i64> %a, %b store <2 x i64> %result, <2 x i64> addrspace(1)* %out @@ -47,8 +54,12 @@ define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, } ; SI-LABEL: @test_v2i64_vreg: +; SI: V_ADD_I32 +; SI: V_ADDC_U32 +; SI: V_ADD_I32 +; SI: V_ADDC_U32 define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { - %tid = call i32 @llvm.SI.tid() readnone + %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid %a = load <2 x i64> addrspace(1)* %a_ptr |
