[GlobalISel][X86] Support vector type G_INSERT legalization/selection.

Summary:
Support vector type G_INSERT legalization/selection.
Split from https://reviews.llvm.org/D33665

Reviewers: qcolombet, t.p.northover, zvi, guyblank

Reviewed By: guyblank

Subscribers: guyblank, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33956

llvm-svn: 305989

4 files changed, 543 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir
new file mode 100644
index 00000000000..8989fb69b41
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir
@@ -0,0 +1,33 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx                -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl  -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
+--- |
+  define void @test_insert_128() {
+    ret void
+  }
+...
+---
+name:            test_insert_128
+# ALL-LABEL: name:  test_insert_128
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+# ALL:               %0(<8 x s32>) = COPY %ymm0
+# ALL-NEXT:          %1(<4 x s32>) = COPY %xmm1
+# ALL-NEXT:          %2(<8 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
+# ALL-NEXT:          %ymm0 = COPY %2(<8 x s32>)
+# ALL-NEXT:          RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<8 x s32>) = COPY %ymm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
+    %ymm0 = COPY %2(<8 x s32>)
+    RET 0, implicit %ymm0
+
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir
new file mode 100644
index 00000000000..777531da4d9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir
@@ -0,0 +1,63 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
+
+--- |
+  define void @test_insert_128() {
+    ret void
+  }
+
+  define void @test_insert_256() {
+    ret void
+  }
+...
+---
+name:            test_insert_128
+# ALL-LABEL: name:  test_insert_128
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+# ALL:          %0(<16 x s32>) = COPY %zmm0
+# ALL-NEXT:     %1(<4 x s32>) = COPY %xmm1
+# ALL-NEXT:     %2(<16 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
+# ALL-NEXT:     %ymm0 = COPY %2(<16 x s32>)
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %zmm0, %ymm1
+
+    %0(<16 x s32>) = COPY %zmm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+
+...
+---
+name:            test_insert_256
+# ALL-LABEL: name:  test_insert_256
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+# ALL:          %0(<16 x s32>) = COPY %zmm0
+# ALL-NEXT:     %1(<8 x s32>) = COPY %ymm1
+# ALL-NEXT:     %2(<16 x s32>) = G_INSERT %0, %1(<8 x s32>), 0
+# ALL-NEXT:     %ymm0 = COPY %2(<16 x s32>)
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %zmm0, %ymm1
+
+    %0(<16 x s32>) = COPY %zmm0
+    %1(<8 x s32>) = COPY %ymm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+
+...
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
new file mode 100644
index 00000000000..923dc22678f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
@@ -0,0 +1,176 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx                -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
+--- |
+  define void @test_insert_128_idx0() {
+    ret void
+  }
+
+  define void @test_insert_128_idx0_undef() {
+    ret void
+  }
+
+  define void @test_insert_128_idx1() {
+    ret void
+  }
+
+  define void @test_insert_128_idx1_undef() {
+    ret void
+  }
+
+...
+---
+name:            test_insert_128_idx0
+# ALL-LABEL: name:  test_insert_128_idx0
+alignment:       4
+legalized:       true
+regBankSelected: true
+# AVX:           registers:
+# AVX-NEXT:        - { id: 0, class: vr256, preferred-register: '' }
+# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
+# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
+#
+# AVX512VL:      registers:
+# AVX512VL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# AVX:               %0 = COPY %ymm0
+# AVX-NEXT:          %1 = COPY %xmm1
+# AVX-NEXT:          %2 = VINSERTF128rr %0, %1, 0
+# AVX-NEXT:          %ymm0 = COPY %2
+# AVX-NEXT:          RET 0, implicit %ymm0
+#
+# AVX512VL:          %0 = COPY %ymm0
+# AVX512VL-NEXT:     %1 = COPY %xmm1
+# AVX512VL-NEXT:     %2 = VINSERTF32x4Z256rr %0, %1, 0
+# AVX512VL-NEXT:     %ymm0 = COPY %2
+# AVX512VL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<8 x s32>) = COPY %ymm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
+    %ymm0 = COPY %2(<8 x s32>)
+    RET 0, implicit %ymm0
+
+...
+---
+name:            test_insert_128_idx0_undef
+# ALL-LABEL: name:  test_insert_128_idx0_undef
+alignment:       4
+legalized:       true
+regBankSelected: true
+# AVX:           registers:
+# AVX-NEXT:        - { id: 0, class: vecr, preferred-register: '' }
+# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
+# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
+#
+# AVX512VL:      registers:
+# AVX512VL-NEXT:   - { id: 0, class: vecr, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:               %1 = COPY %xmm1
+# ALL-NEXT:          undef %2.sub_xmm = COPY %1
+# ALL-NEXT:          %ymm0 = COPY %2
+# ALL-NEXT:          RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<8 x s32>) = IMPLICIT_DEF
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
+    %ymm0 = COPY %2(<8 x s32>)
+    RET 0, implicit %ymm0
+
+...
+---
+name:            test_insert_128_idx1
+# ALL-LABEL: name:  test_insert_128_idx1
+alignment:       4
+legalized:       true
+regBankSelected: true
+# AVX:           registers:
+# AVX-NEXT:        - { id: 0, class: vr256, preferred-register: '' }
+# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
+# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
+#
+# AVX512VL:      registers:
+# AVX512VL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# AVX:               %0 = COPY %ymm0
+# AVX-NEXT:          %1 = COPY %xmm1
+# AVX-NEXT:          %2 = VINSERTF128rr %0, %1, 1
+# AVX-NEXT:          %ymm0 = COPY %2
+# AVX-NEXT:          RET 0, implicit %ymm0
+#
+# AVX512VL:          %0 = COPY %ymm0
+# AVX512VL-NEXT:     %1 = COPY %xmm1
+# AVX512VL-NEXT:     %2 = VINSERTF32x4Z256rr %0, %1, 1
+# AVX512VL-NEXT:     %ymm0 = COPY %2
+# AVX512VL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<8 x s32>) = COPY %ymm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
+    %ymm0 = COPY %2(<8 x s32>)
+    RET 0, implicit %ymm0
+...
+---
+name:            test_insert_128_idx1_undef
+# ALL-LABEL: name:  test_insert_128_idx1_undef
+alignment:       4
+legalized:       true
+regBankSelected: true
+# AVX:           registers:
+# AVX-NEXT:        - { id: 0, class: vr256, preferred-register: '' }
+# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
+# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
+#
+# AVX512VL:      registers:
+# AVX512VL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# AVX:               %0 = IMPLICIT_DEF
+# AVX-NEXT:          %1 = COPY %xmm1
+# AVX-NEXT:          %2 = VINSERTF128rr %0, %1, 1
+# AVX-NEXT:          %ymm0 = COPY %2
+# AVX-NEXT:          RET 0, implicit %ymm0
+#
+# AVX512VL:          %0 = IMPLICIT_DEF
+# AVX512VL-NEXT:     %1 = COPY %xmm1
+# AVX512VL-NEXT:     %2 = VINSERTF32x4Z256rr %0, %1, 1
+# AVX512VL-NEXT:     %ymm0 = COPY %2
+# AVX512VL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<8 x s32>) = IMPLICIT_DEF
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
+    %ymm0 = COPY %2(<8 x s32>)
+    RET 0, implicit %ymm0
+...
+
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
new file mode 100644
index 00000000000..3eddc083805
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
@@ -0,0 +1,271 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
+
+--- |
+  define void @test_insert_128_idx0() {
+    ret void
+  }
+
+  define void @test_insert_128_idx0_undef() {
+    ret void
+  }
+
+  define void @test_insert_128_idx1() {
+    ret void
+  }
+
+  define void @test_insert_128_idx1_undef() {
+    ret void
+  }
+
+  define void @test_insert_256_idx0() {
+    ret void
+  }
+
+  define void @test_insert_256_idx0_undef() {
+    ret void
+  }
+
+  define void @test_insert_256_idx1() {
+    ret void
+  }
+
+  define void @test_insert_256_idx1_undef() {
+    ret void
+  }
+
+...
+---
+name:            test_insert_128_idx0
+# ALL-LABEL: name:  test_insert_128_idx0
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %zmm0
+# ALL-NEXT:     %1 = COPY %xmm1
+# ALL-NEXT:     %2 = VINSERTF32x4Zrr %0, %1, 0
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %zmm0, %ymm1
+
+    %0(<16 x s32>) = COPY %zmm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+
+...
+---
+name:            test_insert_128_idx0_undef
+# ALL-LABEL: name:  test_insert_128_idx0_undef
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vecr, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %1 = COPY %xmm1
+# ALL-NEXT:     undef %2.sub_xmm = COPY %1
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<16 x s32>) = IMPLICIT_DEF
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+
+...
+---
+name:            test_insert_128_idx1
+# ALL-LABEL: name:  test_insert_128_idx1
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %zmm0
+# ALL-NEXT:     %1 = COPY %xmm1
+# ALL-NEXT:     %2 = VINSERTF32x4Zrr %0, %1, 1
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<16 x s32>) = COPY %zmm0
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+...
+---
+name:            test_insert_128_idx1_undef
+# ALL-LABEL: name:  test_insert_128_idx1_undef
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = IMPLICIT_DEF
+# ALL-NEXT:     %1 = COPY %xmm1
+# ALL-NEXT:     %2 = VINSERTF32x4Zrr %0, %1, 1
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<16 x s32>) = IMPLICIT_DEF
+    %1(<4 x s32>) = COPY %xmm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+...
+---
+name:            test_insert_256_idx0
+# ALL-LABEL: name:  test_insert_256_idx0
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %zmm0
+# ALL-NEXT:     %1 = COPY %ymm1
+# ALL-NEXT:     %2 = VINSERTF64x4Zrr %0, %1, 0
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %zmm0, %ymm1
+
+    %0(<16 x s32>) = COPY %zmm0
+    %1(<8 x s32>) = COPY %ymm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+
+...
+---
+name:            test_insert_256_idx0_undef
+# ALL-LABEL: name:  test_insert_256_idx0_undef
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vecr, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %1 = COPY %ymm1
+# ALL-NEXT:     undef %2.sub_ymm = COPY %1
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<16 x s32>) = IMPLICIT_DEF
+    %1(<8 x s32>) = COPY %ymm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+
+...
+---
+name:            test_insert_256_idx1
+# ALL-LABEL: name:  test_insert_256_idx1
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = COPY %zmm0
+# ALL-NEXT:     %1 = COPY %ymm1
+# ALL-NEXT:     %2 = VINSERTF64x4Zrr %0, %1, 1
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<16 x s32>) = COPY %zmm0
+    %1(<8 x s32>) = COPY %ymm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+...
+---
+name:            test_insert_256_idx1_undef
+# ALL-LABEL: name:  test_insert_256_idx1_undef
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+registers:
+  - { id: 0, class: vecr }
+  - { id: 1, class: vecr }
+  - { id: 2, class: vecr }
+# ALL:          %0 = IMPLICIT_DEF
+# ALL-NEXT:     %1 = COPY %ymm1
+# ALL-NEXT:     %2 = VINSERTF64x4Zrr %0, %1, 1
+# ALL-NEXT:     %ymm0 = COPY %2
+# ALL-NEXT:     RET 0, implicit %ymm0
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %ymm0, %ymm1
+
+    %0(<16 x s32>) = IMPLICIT_DEF
+    %1(<8 x s32>) = COPY %ymm1
+    %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
+    %ymm0 = COPY %2(<16 x s32>)
+    RET 0, implicit %ymm0
+...
+