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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-01-24 16:56:23 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-01-24 16:56:23 +0000
commit1b80a146857b3184ff8efe2b0068442d4dc728ae (patch)
tree774c0d11ad81a3c1f1781da80d50b2d24bb6f87a /llvm/test/CodeGen
parentfa6afd1bc6356cdd6810593854054cc2710cb41a (diff)
downloadbcm5719-llvm-1b80a146857b3184ff8efe2b0068442d4dc728ae.tar.gz
bcm5719-llvm-1b80a146857b3184ff8efe2b0068442d4dc728ae.zip
[X86][AVX2] Removed FIXME comment and regenerated test.
The comment talked about replacing vpmovzxwd+vpslld+vpsrad with vpmovsxwd - which isn't valid as we're sign extending a <8 x i1> bool vector not an all/nobits <8 x i16> llvm-svn: 292948
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/pr14204.ll6
1 files changed, 1 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/pr14204.ll b/llvm/test/CodeGen/X86/pr14204.ll
index 3b60ad885d5..ab467d6ad96 100644
--- a/llvm/test/CodeGen/X86/pr14204.ll
+++ b/llvm/test/CodeGen/X86/pr14204.ll
@@ -1,9 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s
-; FIXME: vpmovsxwd should be generated instead of vpmovzxwd followed by
-; SLL/SRA.
-
define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {
; CHECK-LABEL: foo:
; CHECK: # BB#0:
@@ -11,7 +8,6 @@ define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {
; CHECK-NEXT: vpslld $31, %ymm0, %ymm0
; CHECK-NEXT: vpsrad $31, %ymm0, %ymm0
; CHECK-NEXT: retq
-;
%s = sext <8 x i1> %bar to <8 x i32>
ret <8 x i32> %s
}
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