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| author | Hal Finkel <hfinkel@anl.gov> | 2012-12-25 17:22:53 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-12-25 17:22:53 +0000 |
| commit | 1b5ff08d43f0c9d2fe43623990c3cd9e764fb5b0 (patch) | |
| tree | 5668a171af0b44689e94fd468cfbb6c28c4579a3 /llvm/test/CodeGen | |
| parent | 84f46d99939eae16035f048339000e12f715421a (diff) | |
| download | bcm5719-llvm-1b5ff08d43f0c9d2fe43623990c3cd9e764fb5b0.tar.gz bcm5719-llvm-1b5ff08d43f0c9d2fe43623990c3cd9e764fb5b0.zip | |
Expand PPC64 atomic load and store
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
llvm-svn: 171072
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/atomic-2.ll | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/atomic-2.ll b/llvm/test/CodeGen/PowerPC/atomic-2.ll index a427379a8b6..40b4a2eea97 100644 --- a/llvm/test/CodeGen/PowerPC/atomic-2.ll +++ b/llvm/test/CodeGen/PowerPC/atomic-2.ll @@ -24,3 +24,23 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind { ; CHECK: stdcx. ret i64 %tmp } + +define void @atomic_store(i64* %mem, i64 %val) nounwind { +entry: +; CHECK: @atomic_store + store atomic i64 %val, i64* %mem release, align 64 +; CHECK: ldarx +; CHECK: stdcx. + ret void +} + +define i64 @atomic_load(i64* %mem) nounwind { +entry: +; CHECK: @atomic_load + %tmp = load atomic i64* %mem acquire, align 64 +; CHECK: ldarx +; CHECK: stdcx. +; CHECK: stdcx. + ret i64 %tmp +} + |
