[Hexagon] Avoid creating invalid offsets in packetizer

Two memory instructions with a dependency only on the address register
between the two (the first one of them being post-incrememnt) can be
packetized together after the offset on the second was updated to the
incremement value. Make sure that the new offset is valid for the
instruction.

llvm-svn: 328897

1 files changed, 34 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir b/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir
new file mode 100644
index 00000000000..9a142d0ff41
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir
@@ -0,0 +1,34 @@
+# RUN: llc -march=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s
+
+# Make sure that we don't try to packetize the two stores together. The
+# dependence on $r0 could be broken by updating the offset in the storeiri,
+# but then the offset would become invalid for that instruction (it has to
+# be a multiple of 4).
+
+# CHECK: S4_storeiri_io killed renamable $r0, 0, 0
+
+--- |
+  define void @fred() {
+    ret void
+  }
+
+  @g0 = global i8 zeroinitializer, align 2
+  @g1 = global i32 zeroinitializer, align 4
+...
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+ bb.0:
+  successors: %bb.0, %bb.1
+  liveins: $lc0, $r0, $r27
+  $r1 = A2_addi $r0, 24
+  $r0 = S2_storerb_pi $r0, 2, $r27 :: (store 1 into @g0, align 2)
+  S4_storeiri_io killed $r0, 0, 0 :: (store 4 into @g1, align 4)
+  $r0 = A2_tfr killed $r1
+  ENDLOOP0 %bb.0, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+
+ bb.1:
+
+...