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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-10-21 09:58:54 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-10-21 09:58:54 +0000 |
| commit | 0f596814e92dccd4e066b5b8e1c4b33f08a1995a (patch) | |
| tree | 83a63a0acc150ca2d8753d156f8f9102e30aad12 /llvm/test/CodeGen | |
| parent | 55232f0948ab98c285bc65537f03f8e36d2ab9fa (diff) | |
| download | bcm5719-llvm-0f596814e92dccd4e066b5b8e1c4b33f08a1995a.tar.gz bcm5719-llvm-0f596814e92dccd4e066b5b8e1c4b33f08a1995a.zip | |
[mips][msa] Remove copy_u.d and move copy_u.w to MSA64.
Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.
We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.
No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D13472
llvm-svn: 250887
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/Mips/msa/elm_copy.ll | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/elm_copy.ll b/llvm/test/CodeGen/Mips/msa/elm_copy.ll index 2a0d74f4452..251b535fd76 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_copy.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_copy.ll @@ -170,7 +170,8 @@ declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1) ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1) ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) -; MIPS-ANY-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1] +; MIPS32-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1] +; MIPS64-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1] ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES) ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES) ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) @@ -196,7 +197,7 @@ declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind ; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2] ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3] -; MIPS64-DAG: copy_u.d [[RD:\$[0-9]+]], [[WS]][1] +; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1] ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES) ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES) ; MIPS32-DAG: sw [[RD1]], 0([[RES]]) |
