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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-12 21:58:23 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-12 21:58:23 +0000 |
| commit | 0d0d6c2f2515b20ff287107c8d1a07c920558bf1 (patch) | |
| tree | c9fc560d1a209d1631eda3a4877fdc2ae9426d5d /llvm/test/CodeGen | |
| parent | a4f532e0acea879a4b145ffe4d6d26e043a3dc71 (diff) | |
| download | bcm5719-llvm-0d0d6c2f2515b20ff287107c8d1a07c920558bf1.tar.gz bcm5719-llvm-0d0d6c2f2515b20ff287107c8d1a07c920558bf1.zip | |
AMDGPU: Fix invalid copies when copying i1 to phys reg
Insert a VReg_1 virtual register so the i1 workaround pass
can handle it.
llvm-svn: 300113
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inline-asm.ll | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll index 5d49b11f0d4..0d7e07b9a62 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll @@ -196,3 +196,39 @@ entry: call void asm sideeffect "; use $0 ", "{VGPR0_VGPR1}"(i64 123456) ret void } + +; CHECK-LABEL: {{^}}i1_imm_input_phys_vgpr: +; CHECK: v_mov_b32_e32 v0, -1{{$}} +; CHECK: ; use v0 +define amdgpu_kernel void @i1_imm_input_phys_vgpr() { +entry: + call void asm sideeffect "; use $0 ", "{VGPR0}"(i1 true) + ret void +} + +; CHECK-LABEL: {{^}}i1_input_phys_vgpr: +; CHECK: {{buffer|flat}}_load_ubyte [[LOAD:v[0-9]+]] +; CHECK: v_and_b32_e32 [[LOAD]], 1, [[LOAD]] +; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, [[LOAD]] +; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; CHECK: ; use v0 +define amdgpu_kernel void @i1_input_phys_vgpr() { +entry: + %val = load i1, i1 addrspace(1)* undef + call void asm sideeffect "; use $0 ", "{VGPR0}"(i1 %val) + ret void +} + +; FIXME: Should be scheduled to shrink vcc +; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2: +; CHECK: v_cmp_eq_u32_e32 vcc, 1, v0 +; CHECK: v_cmp_eq_u32_e64 s[0:1], 1, v1 +; CHECK: v_cndmask_b32_e64 v0, 0, -1, vcc +; CHECK: v_cndmask_b32_e64 v1, 0, -1, s[0:1] +define amdgpu_kernel void @i1_input_phys_vgpr_x2() { +entry: + %val0 = load volatile i1, i1 addrspace(1)* undef + %val1 = load volatile i1, i1 addrspace(1)* undef + call void asm sideeffect "; use $0 $1 ", "{VGPR0}, {VGPR1}"(i1 %val0, i1 %val1) + ret void +} |
