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| author | Artem Belevich <tra@google.com> | 2016-07-18 19:54:56 +0000 |
|---|---|---|
| committer | Artem Belevich <tra@google.com> | 2016-07-18 19:54:56 +0000 |
| commit | 052b1ed2fd182115fe39abfb36c2615bf5948877 (patch) | |
| tree | 48783b8085e37c209817e9357f4a2614c3179eb1 /llvm/test/CodeGen | |
| parent | a81a44ffd461464e0bc89c611a766eba019bff9b (diff) | |
| download | bcm5719-llvm-052b1ed2fd182115fe39abfb36c2615bf5948877.tar.gz bcm5719-llvm-052b1ed2fd182115fe39abfb36c2615bf5948877.zip | |
[NVPTX] Force minimum alignment of 4 for byval arguments of device-side functions.
Taking address of a byval variable in PTX is legal, but currently runs
into miscompilation by ptxas on sm_50+ (NVIDIA issue 1789042).
Work around the issue by enforcing minimum alignment on byval arguments
of device functions.
The change is a no-op on SASS level for sm_3x where ptxas already aligns
local copy by at least 4.
Differential Revision: https://reviews.llvm.org/D22428
llvm-svn: 275893
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/param-align.ll | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/NVPTX/param-align.ll b/llvm/test/CodeGen/NVPTX/param-align.ll index 84ccb650d40..6d58fda59ae 100644 --- a/llvm/test/CodeGen/NVPTX/param-align.ll +++ b/llvm/test/CodeGen/NVPTX/param-align.ll @@ -23,3 +23,11 @@ define ptx_device void @t3(%struct.float2* byval %x) { ; CHECK: .param .align 4 .b8 t3_param_0[8] ret void } + +;;; Need at least 4-byte alignment in order to avoid miscompilation by +;;; ptxas for sm_50+ +define ptx_device void @t4(i8* byval %x) { +; CHECK: .func t4 +; CHECK: .param .align 4 .b8 t4_param_0[1] + ret void +} |
