AMDGPU: Add new amdgcn intrinsics for cube instructions

More cleanup to try to get all intrinsics using the correct
amdgcn prefix that are as close to the instruction as possible.

llvm-svn: 258786

6 files changed, 107 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/cube.ll b/llvm/test/CodeGen/AMDGPU/cube.ll
new file mode 100644
index 00000000000..ab99af5864e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/cube.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare float @llvm.amdgcn.cubeid(float, float, float) #0
+declare float @llvm.amdgcn.cubesc(float, float, float) #0
+declare float @llvm.amdgcn.cubetc(float, float, float) #0
+declare float @llvm.amdgcn.cubema(float, float, float) #0
+
+declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0
+
+
+; GCN-LABEL: {{^}}cube:
+; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: buffer_store_dwordx4
+define void @cube(<4 x float> addrspace(1)* %out, float %a, float %b, float %c) #1 {
+  %cubeid = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
+  %cubesc = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c)
+  %cubetc = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
+  %cubema = call float @llvm.amdgcn.cubema(float %a, float %b, float %c)
+
+  %vec0 = insertelement <4 x float> undef, float %cubeid, i32 0
+  %vec1 = insertelement <4 x float> %vec0, float %cubesc, i32 1
+  %vec2 = insertelement <4 x float> %vec1, float %cubetc, i32 2
+  %vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3
+  store <4 x float> %vec3, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}legacy_cube:
+; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: buffer_store_dwordx4
+define void @legacy_cube(<4 x float> addrspace(1)* %out, <4 x float> %abcx) #1 {
+  %cube = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %abcx)
+  store <4 x float> %cube, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
+
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll b/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll
index e95a51093cb..c47b3238d4c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll
@@ -1,7 +1,6 @@
-
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-; CHECK: {{^}}cube:
+; CHECK-LABEL: {{^}}cube:
 ; CHECK: CUBE T{{[0-9]}}.X
 ; CHECK: CUBE T{{[0-9]}}.Y
 ; CHECK: CUBE T{{[0-9]}}.Z
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
new file mode 100644
index 00000000000..22bed45ee30
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare float @llvm.amdgcn.cubeid(float, float, float) #0
+
+; GCN-LABEL: {{^}}test_cubeid:
+; GCN: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @test_cubeid(float addrspace(1)* %out, float %a, float %b, float %c) #1 {
+  %result = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
+  store float %result, float addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
new file mode 100644
index 00000000000..565f22c5d5b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare float @llvm.amdgcn.cubema(float, float, float) #0
+
+; GCN-LABEL: {{^}}test_cubema:
+; GCN: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @test_cubema(float addrspace(1)* %out, float %a, float %b, float %c) #1 {
+  %result = call float @llvm.amdgcn.cubema(float %a, float %b, float %c)
+  store float %result, float addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
new file mode 100644
index 00000000000..a3ba3274581
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare float @llvm.amdgcn.cubesc(float, float, float) #0
+
+; GCN-LABEL: {{^}}test_cubesc:
+; GCN: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @test_cubesc(float addrspace(1)* %out, float %a, float %b, float %c) #1 {
+  %result = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c)
+  store float %result, float addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
new file mode 100644
index 00000000000..d3c0f2851ea
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+declare float @llvm.amdgcn.cubetc(float, float, float) #0
+
+; GCN-LABEL: {{^}}test_cubetc:
+; GCN: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define void @test_cubetc(float addrspace(1)* %out, float %a, float %b, float %c) #1 {
+  %result = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
+  store float %result, float addrspace(1)* %out
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }