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| author | Craig Topper <craig.topper@intel.com> | 2019-02-20 05:39:11 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-02-20 05:39:11 +0000 |
| commit | e4025c5eb1f850ddeed71cb92ec10289427184a3 (patch) | |
| tree | 5534c04b075b0255818e50f56886da8a05dcbb7a /llvm/test/CodeGen/X86 | |
| parent | a07f1b94e49cb4ce9e7824ec2fda65108a741090 (diff) | |
| download | bcm5719-llvm-e4025c5eb1f850ddeed71cb92ec10289427184a3.tar.gz bcm5719-llvm-e4025c5eb1f850ddeed71cb92ec10289427184a3.zip | |
[X86] Remove FeatureSlowIncDec from Sandy Bridge and later Intel Core CPUs
Summary:
Inc and Dec were at one point slow on Intel CPUs due to their tendency to cause partial flag stalls on P6 derived CPU cores. This is because these instructions are defined to preserve the carry flag. This partial flag stall issue persisted until Sandy Bridge when flag merging was changed to be handled as a data dependency instead of as a stall until retirement. Sandy Bridge and later CPUs rename the C flag separately from OSPAZ so there is no flag merge needed on INC/DEC to preserve the C flag.
Given these improvements I don't know why INC/DEC was ever considered slow on Sandy Bridge. If anything they should have been disabled on the earlier CPUs instead.
Note after this patch, INC/DEC are still considered slow on Silvermont, Goldmont, Knights Landing and our generic "x86-64" CPU.
Reviewers: spatel, RKSimon, chandlerc
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D58412
llvm-svn: 354436
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/mul-constant-result.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/rdrand.ll | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/mul-constant-result.ll b/llvm/test/CodeGen/X86/mul-constant-result.ll index adac93d3959..61d6b501307 100644 --- a/llvm/test/CodeGen/X86/mul-constant-result.ll +++ b/llvm/test/CodeGen/X86/mul-constant-result.ll @@ -254,7 +254,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: cmovgl %ecx, %eax ; X64-HSW-NEXT: testl %esi, %esi ; X64-HSW-NEXT: cmovel %ecx, %eax -; X64-HSW-NEXT: addl $-1, %edi +; X64-HSW-NEXT: decl %edi ; X64-HSW-NEXT: cmpl $31, %edi ; X64-HSW-NEXT: ja .LBB0_36 ; X64-HSW-NEXT: # %bb.1: diff --git a/llvm/test/CodeGen/X86/rdrand.ll b/llvm/test/CodeGen/X86/rdrand.ll index d6991060e62..1eb614dd40f 100644 --- a/llvm/test/CodeGen/X86/rdrand.ll +++ b/llvm/test/CodeGen/X86/rdrand.ll @@ -94,7 +94,7 @@ define void @loop(i32* %p, i32 %n) nounwind { ; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: rdrandl %esi ; X86-NEXT: movl %esi, (%ecx,%edx,4) -; X86-NEXT: addl $1, %edx +; X86-NEXT: incl %edx ; X86-NEXT: cmpl %edx, %eax ; X86-NEXT: jne .LBB3_2 ; X86-NEXT: .LBB3_3: # %while.end @@ -113,7 +113,7 @@ define void @loop(i32* %p, i32 %n) nounwind { ; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: rdrandl %edx ; X64-NEXT: movl %edx, (%rdi,%rcx,4) -; X64-NEXT: addq $1, %rcx +; X64-NEXT: incq %rcx ; X64-NEXT: cmpl %ecx, %eax ; X64-NEXT: jne .LBB3_2 ; X64-NEXT: .LBB3_3: # %while.end |
