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| author | Sanjay Patel <spatel@rotateright.com> | 2016-10-21 20:16:27 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-21 20:16:27 +0000 |
| commit | ca92c36e014bc806458c0a75e039881030e885e6 (patch) | |
| tree | 9b6cf4803e48729971e38121318f24def5c49f1b /llvm/test/CodeGen/X86 | |
| parent | ae90ad2065786be5168919740100258cf0fe43f9 (diff) | |
| download | bcm5719-llvm-ca92c36e014bc806458c0a75e039881030e885e6.tar.gz bcm5719-llvm-ca92c36e014bc806458c0a75e039881030e885e6.zip | |
[DAG] enhance computeKnownBits to handle SHL with vector splat constant
Also, use APInt to avoid crashing on types larger than vNi64.
llvm-svn: 284874
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-shl.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/negate.ll | 5 |
2 files changed, 3 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll index 3f3871ec5c3..64ed1cea8d4 100644 --- a/llvm/test/CodeGen/X86/combine-shl.ll +++ b/llvm/test/CodeGen/X86/combine-shl.ll @@ -61,16 +61,12 @@ define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) { define <4 x i32> @combine_vec_shl_known_zero0(<4 x i32> %x) { ; SSE-LABEL: combine_vec_shl_known_zero0: ; SSE: # BB#0: -; SSE-NEXT: pxor %xmm1, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7] -; SSE-NEXT: pslld $16, %xmm0 +; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_known_zero0: ; AVX: # BB#0: -; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7] -; AVX-NEXT: vpslld $16, %xmm0, %xmm0 +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq %1 = and <4 x i32> %x, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760> %2 = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16> diff --git a/llvm/test/CodeGen/X86/negate.ll b/llvm/test/CodeGen/X86/negate.ll index e42794d184e..6f07378e0e4 100644 --- a/llvm/test/CodeGen/X86/negate.ll +++ b/llvm/test/CodeGen/X86/negate.ll @@ -35,10 +35,7 @@ define i8 @negate_zero_or_minsigned_nsw(i8 %x) { define <4 x i32> @negate_zero_or_minsigned_nsw_vec(<4 x i32> %x) { ; CHECK-LABEL: negate_zero_or_minsigned_nsw_vec: ; CHECK: # BB#0: -; CHECK-NEXT: pslld $31, %xmm0 -; CHECK-NEXT: pxor %xmm1, %xmm1 -; CHECK-NEXT: psubd %xmm0, %xmm1 -; CHECK-NEXT: movdqa %xmm1, %xmm0 +; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq ; %signbit = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> |
