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| author | Craig Topper <craig.topper@intel.com> | 2017-10-01 23:53:53 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-01 23:53:53 +0000 |
| commit | c20b46da2f48a76f2c2affb290d8073e9ce2aab4 (patch) | |
| tree | eb6efb01957b9f774438ba0671e62d0fa845baa3 /llvm/test/CodeGen/X86 | |
| parent | 00230604d399003acc2ac13c044535ae6b7768ee (diff) | |
| download | bcm5719-llvm-c20b46da2f48a76f2c2affb290d8073e9ce2aab4.tar.gz bcm5719-llvm-c20b46da2f48a76f2c2affb290d8073e9ce2aab4.zip | |
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
Summary:
Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.
For the register®ister form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register®ister form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.
I believe this supercedes D38025 which was trying to switch the register®ister form back to pre-PR22995.
Reviewers: aymanmus, RKSimon, zvi
Reviewed By: aymanmus
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38120
llvm-svn: 314639
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/absolute-bit-mask.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/testl-commute.ll | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/absolute-bit-mask.ll b/llvm/test/CodeGen/X86/absolute-bit-mask.ll index 6e119494ac3..818952dc453 100644 --- a/llvm/test/CodeGen/X86/absolute-bit-mask.ll +++ b/llvm/test/CodeGen/X86/absolute-bit-mask.ll @@ -43,7 +43,7 @@ f: define void @foo64(i64* %ptr) { %load = load i64, i64* %ptr ; CHECK: movabsq $bit_mask64, %rax - ; CHECK: testq (%rdi), %rax + ; CHECK: testq %rax, (%rdi) %and = and i64 %load, ptrtoint (i8* @bit_mask64 to i64) %icmp = icmp eq i64 %and, 0 br i1 %icmp, label %t, label %f diff --git a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir index efc384d36d0..ee07571d17b 100644 --- a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir +++ b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir @@ -292,7 +292,7 @@ body: | %rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags %rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags %rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8) - TEST32rm killed %eax, killed %rcx, 4, killed %rdx, 0, _, implicit-def %eflags :: (load 4) + TEST32mr killed %rcx, 4, killed %rdx, 0, _, killed %eax, implicit-def %eflags :: (load 4) JNE_1 %bb.2, implicit %eflags JMP_1 %bb.3 diff --git a/llvm/test/CodeGen/X86/testl-commute.ll b/llvm/test/CodeGen/X86/testl-commute.ll index a9a9e581d99..43e095aecd0 100644 --- a/llvm/test/CodeGen/X86/testl-commute.ll +++ b/llvm/test/CodeGen/X86/testl-commute.ll @@ -9,7 +9,7 @@ target triple = "x86_64-apple-darwin7" define i32 @test(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: @@ -30,7 +30,7 @@ bb1: ; preds = %entry define i32 @test2(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test2: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: @@ -51,7 +51,7 @@ bb1: ; preds = %entry define i32 @test3(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test3: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: |
