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| author | Sanjay Patel <spatel@rotateright.com> | 2019-02-06 00:19:56 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-02-06 00:19:56 +0000 |
| commit | 997b2aba58ddbf6038fc52f20d5ed94edcfe8d00 (patch) | |
| tree | af8b1d2039724d0a31e4fc70f53d25412580b5ae /llvm/test/CodeGen/X86 | |
| parent | 4367587fc6f2ceb6699359cec08a689eeaa153c9 (diff) | |
| download | bcm5719-llvm-997b2aba58ddbf6038fc52f20d5ed94edcfe8d00.tar.gz bcm5719-llvm-997b2aba58ddbf6038fc52f20d5ed94edcfe8d00.zip | |
[x86] add tests for extract+sitofp; NFC
llvm-svn: 353249
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_int_to_fp.ll | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vec_int_to_fp.ll b/llvm/test/CodeGen/X86/vec_int_to_fp.ll index 15895b4fd20..56b4e64d1d2 100644 --- a/llvm/test/CodeGen/X86/vec_int_to_fp.ll +++ b/llvm/test/CodeGen/X86/vec_int_to_fp.ll @@ -5571,6 +5571,55 @@ define float @extract0_sitofp_v4i32_f32(<4 x i32> %x) nounwind { ret float %r } +define float @extract0_sitofp_v4i32_f32i_multiuse1(<4 x i32> %x) nounwind { +; SSE-LABEL: extract0_sitofp_v4i32_f32i_multiuse1: +; SSE: # %bb.0: +; SSE-NEXT: movd %xmm0, %eax +; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: cvtsi2ssl %eax, %xmm0 +; SSE-NEXT: incl %eax +; SSE-NEXT: cvtsi2ssl %eax, %xmm1 +; SSE-NEXT: divss %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: extract0_sitofp_v4i32_f32i_multiuse1: +; AVX: # %bb.0: +; AVX-NEXT: vmovd %xmm0, %eax +; AVX-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0 +; AVX-NEXT: incl %eax +; AVX-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm1 +; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %e = extractelement <4 x i32> %x, i32 0 + %f = sitofp i32 %e to float + %e1 = add i32 %e, 1 + %f1 = sitofp i32 %e1 to float + %r = fdiv float %f, %f1 + ret float %r +} + +define float @extract0_sitofp_v4i32_f32_multiuse2(<4 x i32> %x, i32* %p) nounwind { +; SSE-LABEL: extract0_sitofp_v4i32_f32_multiuse2: +; SSE: # %bb.0: +; SSE-NEXT: movd %xmm0, %eax +; SSE-NEXT: cvtsi2ssl %eax, %xmm1 +; SSE-NEXT: movd %xmm0, (%rdi) +; SSE-NEXT: movaps %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: extract0_sitofp_v4i32_f32_multiuse2: +; AVX: # %bb.0: +; AVX-NEXT: vmovd %xmm0, %eax +; AVX-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm1 +; AVX-NEXT: vmovd %xmm0, (%rdi) +; AVX-NEXT: vmovaps %xmm1, %xmm0 +; AVX-NEXT: retq + %e = extractelement <4 x i32> %x, i32 0 + %r = sitofp i32 %e to float + store i32 %e, i32* %p + ret float %r +} + define double @extract0_sitofp_v4i32_f64(<4 x i32> %x) nounwind { ; SSE-LABEL: extract0_sitofp_v4i32_f64: ; SSE: # %bb.0: |

