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authorJoey Gouly <joey.gouly@arm.com>2013-08-21 17:14:31 +0000
committerJoey Gouly <joey.gouly@arm.com>2013-08-21 17:14:31 +0000
commit6c6a01de3bd6d130935a8a3905d351805e4eb0e7 (patch)
treee74e820f9b1bbe4516c8367a54cf9c1e848987cd /llvm/test/CodeGen/X86
parent6929064005e40e0ef6cb347faadb38bfe3f4a47d (diff)
downloadbcm5719-llvm-6c6a01de3bd6d130935a8a3905d351805e4eb0e7.tar.gz
bcm5719-llvm-6c6a01de3bd6d130935a8a3905d351805e4eb0e7.zip
Add -mcpu to two X86 tests.
These tests are failing on Haswell CPUs due to different instruction selection. llvm-svn: 188908
Diffstat (limited to 'llvm/test/CodeGen/X86')
-rw-r--r--llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll2
-rw-r--r--llvm/test/CodeGen/X86/i128-mul.ll2
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll b/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
index 7a3d72dd4b0..1ec9c70d570 100644
--- a/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
+++ b/llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep sarl | not grep esp
+; RUN: llc < %s -march=x86 -mcpu=corei7 | grep sarl | not grep esp
define signext i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) {
entry:
diff --git a/llvm/test/CodeGen/X86/i128-mul.ll b/llvm/test/CodeGen/X86/i128-mul.ll
index c0b85dfd211..8cfda85ce46 100644
--- a/llvm/test/CodeGen/X86/i128-mul.ll
+++ b/llvm/test/CodeGen/X86/i128-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
; PR1198
define i64 @foo(i64 %x, i64 %y) {
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