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| author | Anton Yartsev <anton.yartsev@gmail.com> | 2017-07-04 01:08:55 +0000 |
|---|---|---|
| committer | Anton Yartsev <anton.yartsev@gmail.com> | 2017-07-04 01:08:55 +0000 |
| commit | 66d32c5e06738f851ce0a00d519a9481b52922e9 (patch) | |
| tree | 9f4e6ca67e6c9614866085215ff6d9c34beff16d /llvm/test/CodeGen/X86 | |
| parent | 61118e7ecd648b9faf01b4febd541305b94730c8 (diff) | |
| download | bcm5719-llvm-66d32c5e06738f851ce0a00d519a9481b52922e9.tar.gz bcm5719-llvm-66d32c5e06738f851ce0a00d519a9481b52922e9.zip | |
[legalize-types] Clean up softening machinery.
The patch makes SoftenFloatResult/Operand logic just the same as all other legalization routines have: SoftenFloatResult() now fills the SoftenFloats map and SoftenFloatOperand() perform all needed replacements. This prevents softening mashinery from leaving stale entries in SoftenFloats map (that resulted in errors during the legalize type checking) and clarifies softening. The patch replaces https://reviews.llvm.org/D29265.
Differential Revision: https://reviews.llvm.org/D31946
llvm-svn: 307053
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll b/llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll new file mode 100644 index 00000000000..0461ee809ef --- /dev/null +++ b/llvm/test/CodeGen/X86/soft-fp-legal-in-HW-reg.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -mtriple=x86_64-linux-android -mattr=+mmx -enable-legalize-types-checking | FileCheck %s +; +; D31946 +; Check that we dont end up with the ""LLVM ERROR: Cannot select" error. +; Additionally ensure that the output code actually put fp128 values in SSE registers. + +declare fp128 @llvm.fabs.f128(fp128) +declare fp128 @llvm.copysign.f128(fp128, fp128) + +define fp128 @TestSelect(fp128 %a, fp128 %b) { + %cmp = fcmp ogt fp128 %a, %b + %sub = fsub fp128 %a, %b + %res = select i1 %cmp, fp128 %sub, fp128 0xL00000000000000000000000000000000 + ret fp128 %res +; CHECK-LABEL: TestSelect: +; CHECK movaps 16(%rsp), %xmm1 +; CHECK-NEXT callq __subtf3 +; CHECK-NEXT testl %ebx, %ebx +; CHECK-NEXT jg .LBB0_2 +; CHECK-NEXT # BB#1: +; CHECK-NEXT movaps .LCPI0_0(%rip), %xmm0 +; CHECK-NEXT .LBB0_2: +; CHECK-NEXT addq $32, %rsp +; CHECK-NEXT popq %rbx +; CHECK-NEXT retq +} + +define fp128 @TestFabs(fp128 %a) { + %res = call fp128 @llvm.fabs.f128(fp128 %a) + ret fp128 %res +; CHECK-LABEL: TestFabs: +; CHECK andps .LCPI1_0(%rip), %xmm0 +; CHECK-NEXT retq +} + +define fp128 @TestCopysign(fp128 %a, fp128 %b) { + %res = call fp128 @llvm.copysign.f128(fp128 %a, fp128 %b) + ret fp128 %res +; CHECK-LABEL: TestCopysign: +; CHECK andps .LCPI2_1(%rip), %xmm0 +; CHECK-NEXT orps %xmm1, %xmm0 +; CHECK-NEXT retq +} + +define fp128 @TestFneg(fp128 %a) { + %mul = fmul fp128 %a, %a + %res = fsub fp128 0xL00000000000000008000000000000000, %mul + ret fp128 %res +; CHECK-LABEL: TestFneg: +; CHECK movaps %xmm0, %xmm1 +; CHECK-NEXT callq __multf3 +; CHECK-NEXT xorps .LCPI3_0(%rip), %xmm0 +; CHECK-NEXT popq %rax +; CHECK-NEXT retq +} |

