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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-22 20:21:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-22 20:21:36 +0000 |
| commit | 629d12de70959f49f0b8f78eb9e6e217103a24c7 (patch) | |
| tree | b4b1bfc0306ed7cbc5a790a87418dc1e473f3d7e /llvm/test/CodeGen/X86 | |
| parent | 66ac1d61526268d1f81db8ed1d5caccfed2452ec (diff) | |
| download | bcm5719-llvm-629d12de70959f49f0b8f78eb9e6e217103a24c7.tar.gz bcm5719-llvm-629d12de70959f49f0b8f78eb9e6e217103a24c7.zip | |
DAGCombiner: Relax alignment restriction when changing load type
If the target allows the alignment, this should still be OK.
llvm-svn: 267209
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-mask-op.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/masked_gather_scatter.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll index ea6a7af34ff..de0c97cf0b5 100644 --- a/llvm/test/CodeGen/X86/avx512-mask-op.ll +++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll @@ -53,7 +53,7 @@ define void @mask16_mem(i16* %ptr) { define void @mask8_mem(i8* %ptr) { ; KNL-LABEL: mask8_mem: ; KNL: ## BB#0: -; KNL-NEXT: movb (%rdi), %al +; KNL-NEXT: movzbw (%rdi), %ax ; KNL-NEXT: kmovw %eax, %k0 ; KNL-NEXT: knotw %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax @@ -951,7 +951,7 @@ define <16 x i32> @load_16i1(<16 x i1>* %a) { define <2 x i16> @load_2i1(<2 x i1>* %a) { ; KNL-LABEL: load_2i1: ; KNL: ## BB#0: -; KNL-NEXT: movb (%rdi), %al +; KNL-NEXT: movzbw (%rdi), %ax ; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; KNL-NEXT: retq @@ -969,7 +969,7 @@ define <2 x i16> @load_2i1(<2 x i1>* %a) { define <4 x i16> @load_4i1(<4 x i1>* %a) { ; KNL-LABEL: load_4i1: ; KNL: ## BB#0: -; KNL-NEXT: movb (%rdi), %al +; KNL-NEXT: movzbw (%rdi), %ax ; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; KNL-NEXT: vpmovqd %zmm0, %ymm0 diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter.ll b/llvm/test/CodeGen/X86/masked_gather_scatter.ll index ed88be0fd14..f153338aa41 100644 --- a/llvm/test/CodeGen/X86/masked_gather_scatter.ll +++ b/llvm/test/CodeGen/X86/masked_gather_scatter.ll @@ -291,7 +291,7 @@ define <8 x i32> @test7(i32* %base, <8 x i32> %ind, i8 %mask) { ; KNL_32-LABEL: test7: ; KNL_32: # BB#0: ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax -; KNL_32-NEXT: movb {{[0-9]+}}(%esp), %cl +; KNL_32-NEXT: movzbw {{[0-9]+}}(%esp), %cx ; KNL_32-NEXT: kmovw %ecx, %k1 ; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm0 ; KNL_32-NEXT: kmovw %k1, %k2 diff --git a/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll b/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll index 3b6582fa04f..fafd796d299 100644 --- a/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll +++ b/llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll @@ -234,7 +234,7 @@ define <8 x i64> @merge_8i64_i64_1u3u5zu8(i64* %ptr) nounwind uwtable noinline s ; X32-AVX512F-LABEL: merge_8i64_i64_1u3u5zu8: ; X32-AVX512F: # BB#0: ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-AVX512F-NEXT: vmovdqu32 8(%eax), %zmm0 +; X32-AVX512F-NEXT: vmovdqu64 8(%eax), %zmm0 ; X32-AVX512F-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; X32-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = <0,0,u,u,2,0,u,u,4,0,13,0,u,u,7,0> ; X32-AVX512F-NEXT: vpermt2q %zmm1, %zmm2, %zmm0 |
