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| author | Vivek Pandya <vivekvpandya@gmail.com> | 2017-06-06 08:16:19 +0000 |
|---|---|---|
| committer | Vivek Pandya <vivekvpandya@gmail.com> | 2017-06-06 08:16:19 +0000 |
| commit | 56d87ef5d7c3b3f53cafd2a360b949b39bc88733 (patch) | |
| tree | 9b36e6cc388489ee0c0a4794ba2096366d1f8a73 /llvm/test/CodeGen/X86 | |
| parent | 6c41bb1bdfe248300a817fceafadfc10dd9eec86 (diff) | |
| download | bcm5719-llvm-56d87ef5d7c3b3f53cafd2a360b949b39bc88733.tar.gz bcm5719-llvm-56d87ef5d7c3b3f53cafd2a360b949b39bc88733.zip | |
[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.
If -simplify-mir option is passed then MIRPrinter will not print such fields.
This change also required some lit test cases in CodeGen directory to be changed.
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D32304
llvm-svn: 304779
Diffstat (limited to 'llvm/test/CodeGen/X86')
34 files changed, 704 insertions, 704 deletions
diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll index eddb7025cfb..00aa7cf84e5 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll @@ -11,8 +11,8 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, ; ALL-LABEL: name: test_i8_args_8 ; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false -; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false +; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true, +; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true, ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d ; X64: [[ARG1:%[0-9]+]](s8) = COPY %edi ; X64-NEXT: %{{[0-9]+}}(s8) = COPY %esi @@ -26,14 +26,14 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, ; X64-NEXT: [[ARG8:%[0-9]+]](s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0) ; X32: fixedStack: -; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 1, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 1, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 1, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 1, alignment: 4, isImmutable: true, +; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 1, alignment: 8, isImmutable: true, +; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 1, alignment: 4, isImmutable: true, +; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 1, alignment: 16, isImmutable: true, +; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 1, alignment: 4, isImmutable: true, +; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true, +; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 1, alignment: 4, isImmutable: true, +; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true, ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -77,8 +77,8 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, ; ALL-LABEL: name: test_i32_args_8 ; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false -; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false +; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true, +; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true, ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d ; X64: [[ARG1:%[0-9]+]](s32) = COPY %edi ; X64-NEXT: %{{[0-9]+}}(s32) = COPY %esi @@ -92,14 +92,14 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, ; X64-NEXT: [[ARG8:%[0-9]+]](s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0) ; X32: fixedStack: -; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true, +; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true, +; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true, +; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true, ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -142,8 +142,8 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, ; ALL-LABEL: name: test_i64_args_8 ; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false -; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false +; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true, +; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true, ; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9 ; X64: [[ARG1:%[0-9]+]](s64) = COPY %rdi ; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rsi @@ -157,22 +157,22 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, ; X64-NEXT: [[ARG8:%[0-9]+]](s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0) ; X32: fixedStack: -; X32: id: [[STACK60:[0-9]+]], offset: 60, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK56:[0-9]+]], offset: 56, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK52:[0-9]+]], offset: 52, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK48:[0-9]+]], offset: 48, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK44:[0-9]+]], offset: 44, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK40:[0-9]+]], offset: 40, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK36:[0-9]+]], offset: 36, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK32:[0-9]+]], offset: 32, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false } -; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK60:[0-9]+]], type: default, offset: 60, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK56:[0-9]+]], type: default, offset: 56, size: 4, alignment: 8, isImmutable: true, +; X32: id: [[STACK52:[0-9]+]], type: default, offset: 52, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK48:[0-9]+]], type: default, offset: 48, size: 4, alignment: 16, isImmutable: true, +; X32: id: [[STACK44:[0-9]+]], type: default, offset: 44, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK40:[0-9]+]], type: default, offset: 40, size: 4, alignment: 8, isImmutable: true, +; X32: id: [[STACK36:[0-9]+]], type: default, offset: 36, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK32:[0-9]+]], type: default, offset: 32, size: 4, alignment: 16, isImmutable: true, +; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true, +; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true, +; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true, +; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true, ; X32: [[ARG1L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1L:%[0-9]+]](s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) @@ -249,8 +249,8 @@ define float @test_float_args(float %arg1, float %arg2) { ; X64-NEXT: RET 0, implicit %xmm0 ; X32: fixedStack: -; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true, +; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true, ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -270,8 +270,8 @@ define double @test_double_args(double %arg1, double %arg2) { ; X64-NEXT: RET 0, implicit %xmm0 ; X32: fixedStack: -; X32: id: [[STACK4:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false } -; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false } +; X32: id: [[STACK4:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true, +; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true, ; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ; X32-NEXT: [[ARG1:%[0-9]+]](s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0) ; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] @@ -322,7 +322,7 @@ define i32 * @test_memop_i32(i32 * %p1) { ;X64-NEXT: RET 0, implicit %rax ;X32: fixedStack: -;X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +;X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true, ;X32: %1(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] ;X32-NEXT: %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) ;X32-NEXT: %eax = COPY %0(p0) diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir index 0d66a638410..682d01e66fa 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir @@ -24,9 +24,9 @@ alignment: 4 legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _ } -# CHECK-NEXT: - { id: 1, class: _ } -# CHECK-NEXT: - { id: 2, class: _ } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ alignment: 4 legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _ } -# CHECK-NEXT: - { id: 1, class: _ } -# CHECK-NEXT: - { id: 2, class: _ } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -88,9 +88,9 @@ alignment: 4 legalized: false regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: _ } -# CHECK-NEXT: - { id: 1, class: _ } -# CHECK-NEXT: - { id: 2, class: _ } +# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir index be62832b008..effd26e9866 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir @@ -26,9 +26,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -86,9 +86,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir index d99303c3ba3..5ae8132156d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir @@ -26,9 +26,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,9 +56,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -86,9 +86,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir index 24eefd30c2a..71ea313c4c7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir @@ -28,9 +28,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -58,9 +58,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -88,9 +88,9 @@ alignment: 4 legalized: false regBankSelected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: _ } -# ALL-NEXT: - { id: 1, class: _ } -# ALL-NEXT: - { id: 2, class: _ } +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: _, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: _, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir index cc03f3a57f0..ca238b29c2d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir @@ -33,8 +33,8 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_mul_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } +# CHECK: - { id: 0, class: vecr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -56,8 +56,8 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } +# CHECK: - { id: 0, class: vecr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -79,8 +79,8 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_sub_vec256 # CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } +# CHECK: - { id: 0, class: vecr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -100,8 +100,8 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: vecr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -122,8 +122,8 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr } -# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir index 278413ad38e..c94ecc8e9a8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir @@ -33,8 +33,8 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr } -# CHECK-NEXT: - { id: 1, class: vecr } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -53,8 +53,8 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr } -# CHECK-NEXT: - { id: 1, class: vecr } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -73,8 +73,8 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr } -# CHECK-NEXT: - { id: 1, class: vecr } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -93,8 +93,8 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: vecr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -115,8 +115,8 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr } -# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir index a115d1fa325..b74e03f0fe7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir @@ -14,11 +14,11 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -# CHECK-NEXT: - { id: 4, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir index 1ea922ee475..7bcc57aef4a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -145,9 +145,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_i8 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -# CHECK: - { id: 2, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -172,9 +172,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_i16 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -# CHECK: - { id: 2, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -199,9 +199,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -# CHECK: - { id: 2, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -226,9 +226,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_i64 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -# CHECK: - { id: 2, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -253,14 +253,14 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_mul_gpr # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -# CHECK: - { id: 2, class: gpr } -# CHECK: - { id: 3, class: gpr } -# CHECK: - { id: 4, class: gpr } -# CHECK: - { id: 5, class: gpr } -# CHECK: - { id: 6, class: gpr } -# CHECK: - { id: 7, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } +# CHECK: - { id: 2, class: gpr, preferred-register: '' } +# CHECK: - { id: 3, class: gpr, preferred-register: '' } +# CHECK: - { id: 4, class: gpr, preferred-register: '' } +# CHECK: - { id: 5, class: gpr, preferred-register: '' } +# CHECK: - { id: 6, class: gpr, preferred-register: '' } +# CHECK: - { id: 7, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -292,9 +292,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_float # CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } -# CHECK: - { id: 2, class: vecr } +# CHECK: - { id: 0, class: vecr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -319,9 +319,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_double # CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } -# CHECK: - { id: 2, class: vecr } +# CHECK: - { id: 0, class: vecr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -346,9 +346,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_v4i32 # CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } -# CHECK: - { id: 2, class: vecr } +# CHECK: - { id: 0, class: vecr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -373,9 +373,9 @@ selected: false tracksRegLiveness: true # CHECK-LABEL: name: test_add_v4f32 # CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } -# CHECK: - { id: 2, class: vecr } +# CHECK: - { id: 0, class: vecr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } +# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -399,8 +399,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_load_i8 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -422,8 +422,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_load_i16 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -445,8 +445,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_load_i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -469,8 +469,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_load_i64 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -492,8 +492,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_load_float # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -515,8 +515,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_load_double # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -538,8 +538,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_load_v4i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: vecr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -561,8 +561,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_store_i32 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -585,8 +585,8 @@ regBankSelected: false selected: false # CHECK-LABEL: name: test_store_i64 # CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } +# CHECK: - { id: 0, class: gpr, preferred-register: '' } +# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -610,12 +610,12 @@ selected: false # CHECK-LABEL: name: test_store_float # CHECK: registers: -# FAST-NEXT: - { id: 0, class: vecr } -# FAST-NEXT: - { id: 1, class: gpr } -# FAST-NEXT: - { id: 2, class: gpr } +# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# GREEDY-NEXT: - { id: 0, class: vecr } -# GREEDY-NEXT: - { id: 1, class: gpr } +# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } @@ -647,12 +647,12 @@ selected: false # CHECK-LABEL: name: test_store_double # CHECK: registers: -# FAST-NEXT: - { id: 0, class: vecr } -# FAST-NEXT: - { id: 1, class: gpr } -# FAST-NEXT: - { id: 2, class: gpr } +# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# GREEDY-NEXT: - { id: 0, class: vecr } -# GREEDY-NEXT: - { id: 1, class: gpr } +# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' } +# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } @@ -682,10 +682,10 @@ alignment: 4 legalized: true # CHECK-LABEL: name: constInt_check # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -706,10 +706,10 @@ alignment: 4 legalized: true # CHECK-LABEL: name: trunc_check # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -729,11 +729,11 @@ name: test_gep legalized: true # CHECK-LABEL: name: test_gep # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -# CHECK-NEXT: - { id: 4, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -757,9 +757,9 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -782,9 +782,9 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -807,9 +807,9 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -832,9 +832,9 @@ alignment: 4 legalized: true regBankSelected: false # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir index a39702340bc..4f7b6ec72d5 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir @@ -32,19 +32,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128 } -# AVX512VL-NEXT: - { id: 1, class: vr128 } -# AVX512VL-NEXT: - { id: 2, class: vr128 } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -74,19 +74,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128 } -# AVX512VL-NEXT: - { id: 1, class: vr128 } -# AVX512VL-NEXT: - { id: 2, class: vr128 } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -116,19 +116,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -158,19 +158,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir index 7556c210412..143fd942297 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir @@ -30,19 +30,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256 } -# AVX512VL-NEXT: - { id: 1, class: vr256 } -# AVX512VL-NEXT: - { id: 2, class: vr256 } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -70,19 +70,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256 } -# AVX512VL-NEXT: - { id: 1, class: vr256 } -# AVX512VL-NEXT: - { id: 2, class: vr256 } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -110,19 +110,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x } -# AVX512VL-NEXT: - { id: 1, class: vr256x } -# AVX512VL-NEXT: - { id: 2, class: vr256x } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -150,19 +150,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x } -# AVX512VL-NEXT: - { id: 1, class: vr256x } -# AVX512VL-NEXT: - { id: 2, class: vr256x } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir index e90be4e996f..6a0cd32eefd 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir @@ -31,9 +31,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -57,9 +57,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -83,9 +83,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -109,9 +109,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir index 8710aaa61a2..0b864f41736 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir @@ -13,16 +13,16 @@ alignment: 4 legalized: true regBankSelected: true # X32: registers: -# X32-NEXT: - { id: 0, class: gr32 } -# X32-NEXT: - { id: 1, class: gr32 } -# X32-NEXT: - { id: 2, class: gr32 } -# X32-NEXT: - { id: 3, class: gr32 } -# X32-NEXT: - { id: 4, class: gpr } -# X32-NEXT: - { id: 5, class: gr32 } -# X32-NEXT: - { id: 6, class: gr32 } -# X32-NEXT: - { id: 7, class: gr32 } -# X32-NEXT: - { id: 8, class: gr32 } -# X32-NEXT: - { id: 9, class: gpr } +# X32-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 4, class: gpr, preferred-register: '' } +# X32-NEXT: - { id: 5, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 6, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 7, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 8, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 9, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add.mir index 7337ce12c39..78e6bb6913a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add.mir @@ -51,9 +51,9 @@ name: test_add_i64 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64 } -# ALL-NEXT: - { id: 1, class: gr64 } -# ALL-NEXT: - { id: 2, class: gr64 } +# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -78,9 +78,9 @@ name: test_add_i32 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -106,9 +106,9 @@ legalized: true regBankSelected: true selected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16 } -# ALL-NEXT: - { id: 1, class: gr16 } -# ALL-NEXT: - { id: 2, class: gr16 } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -135,9 +135,9 @@ legalized: true regBankSelected: true selected: false # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# ALL-NEXT: - { id: 1, class: gr8 } -# ALL-NEXT: - { id: 2, class: gr8 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -165,12 +165,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr32 } -# NO_AVX512F-NEXT: - { id: 1, class: fr32 } -# NO_AVX512F-NEXT: - { id: 2, class: fr32 } -# AVX512ALL-NEXT: - { id: 0, class: fr32x } -# AVX512ALL-NEXT: - { id: 1, class: fr32x } -# AVX512ALL-NEXT: - { id: 2, class: fr32x } +# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -200,12 +200,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr64 } -# NO_AVX512F-NEXT: - { id: 1, class: fr64 } -# NO_AVX512F-NEXT: - { id: 2, class: fr64 } -# AVX512ALL-NEXT: - { id: 0, class: fr64x } -# AVX512ALL-NEXT: - { id: 1, class: fr64x } -# AVX512ALL-NEXT: - { id: 2, class: fr64x } +# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -235,12 +235,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128 } -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -271,12 +271,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128 } -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir index a92c388c1db..64c8cb6b823 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir @@ -87,11 +87,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr8 } -# CHECK-NEXT: - { id: 1, class: gr8 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -124,11 +124,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr16 } -# CHECK-NEXT: - { id: 1, class: gr16 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -161,11 +161,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64 } -# CHECK-NEXT: - { id: 1, class: gr64 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -198,11 +198,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -235,11 +235,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -272,11 +272,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -309,11 +309,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -346,11 +346,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -383,11 +383,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -420,11 +420,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -457,11 +457,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -494,11 +494,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -531,11 +531,11 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr32 } -# CHECK-NEXT: - { id: 2, class: gr8 } -# CHECK-NEXT: - { id: 3, class: gr32 } -# CHECK-NEXT: - { id: 4, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir index 162de026443..7902a5084ce 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir @@ -33,7 +33,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i8 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr8 } +# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -52,7 +52,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i16 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr16 } +# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -71,7 +71,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -90,7 +90,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i64 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64 } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -110,7 +110,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i64_u32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64 } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -129,7 +129,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i64_i32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64 } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir index d1a3abfd0f9..edb467b2bf9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -25,10 +25,10 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# ALL-NEXT: - { id: 1, class: gr8 } -# ALL-NEXT: - { id: 2, class: gr64 } -# ALL-NEXT: - { id: 3, class: gr64 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 3, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -57,8 +57,8 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# ALL-NEXT: - { id: 1, class: gr64 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -83,8 +83,8 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16 } -# ALL-NEXT: - { id: 1, class: gr64 } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir index dccc20e5710..b52f1f6fa62 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -35,9 +35,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -63,8 +63,8 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -89,8 +89,8 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16 } -# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -115,8 +115,8 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -141,8 +141,8 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16 } -# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir b/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir index c8a4dc80cb2..61c76623003 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir @@ -14,9 +14,9 @@ regBankSelected: true selected: false # CHECK-LABEL: name: test_gep_i32 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64 } -# CHECK-NEXT: - { id: 1, class: gr64_nosp } -# CHECK-NEXT: - { id: 2, class: gr64 } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir b/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir index 7a77864091d..47fe6ef672b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir @@ -13,10 +13,10 @@ name: test_add_i8 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# INC-NEXT: - { id: 1, class: gpr } -# ADD-NEXT: - { id: 1, class: gr8 } -# ALL-NEXT: - { id: 2, class: gr8 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# INC-NEXT: - { id: 1, class: gpr, preferred-register: '' } +# ADD-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir index 539520c0b8f..9128f19b1d2 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir @@ -29,7 +29,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i32_1 # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -47,7 +47,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i32_1_optsize # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -65,7 +65,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i32_1b # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: @@ -83,7 +83,7 @@ regBankSelected: true selected: false # CHECK-LABEL: name: const_i32_1_optsizeb # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } # CHECK: body: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir index 8e6a2771db6..09f414b48a8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir @@ -49,9 +49,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr8 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -79,9 +79,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr16 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -109,9 +109,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -139,10 +139,10 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } -# ALL-NEXT: - { id: 3, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -176,10 +176,10 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } -# ALL-NEXT: - { id: 3, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -213,10 +213,10 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } -# ALL-NEXT: - { id: 3, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -250,9 +250,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -280,10 +280,10 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } -# ALL-NEXT: - { id: 3, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir index b57c9b0cca9..6d03d7525d2 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir @@ -91,8 +91,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr8 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr8, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -115,8 +115,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr16 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr16, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -139,8 +139,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr32 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr32, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -163,8 +163,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr64 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -187,8 +187,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr32 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr32, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -211,9 +211,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# NO_AVX512F: - { id: 1, class: fr32 } -# AVX512ALL: - { id: 1, class: fr32x } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 1, class: fr32, preferred-register: '' } +# AVX512ALL: - { id: 1, class: fr32x, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -238,8 +238,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr64 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -262,9 +262,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# NO_AVX512F: - { id: 1, class: fr64 } -# AVX512ALL: - { id: 1, class: fr64x } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 1, class: fr64, preferred-register: '' } +# AVX512ALL: - { id: 1, class: fr64x, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -289,8 +289,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr32 } -# ALL: - { id: 1, class: gr64 } +# ALL: - { id: 0, class: gr32, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %edi @@ -315,8 +315,8 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr64 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0 = COPY %rdi @@ -341,9 +341,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: fr32x } -# ALL: - { id: 1, class: gr64 } -# ALL: - { id: 2, class: gr32 } +# ALL: - { id: 0, class: fr32x, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 2, class: gr32, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } @@ -371,9 +371,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: fr32 } -# AVX512ALL: - { id: 0, class: fr32x } -# ALL: - { id: 1, class: gr64 } +# NO_AVX512F: - { id: 0, class: fr32, preferred-register: '' } +# AVX512ALL: - { id: 0, class: fr32x, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 @@ -400,9 +400,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: fr64x } -# ALL: - { id: 1, class: gr64 } -# ALL: - { id: 2, class: gr64 } +# ALL: - { id: 0, class: fr64x, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } +# ALL: - { id: 2, class: gr64, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } - { id: 2, class: gpr } @@ -430,9 +430,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: fr64 } -# AVX512ALL: - { id: 0, class: fr64x } -# ALL: - { id: 1, class: gr64 } +# NO_AVX512F: - { id: 0, class: fr64, preferred-register: '' } +# AVX512ALL: - { id: 0, class: fr64x, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 @@ -460,8 +460,8 @@ legalized: true regBankSelected: true selected: false registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr64 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1) @@ -483,8 +483,8 @@ legalized: true regBankSelected: true selected: false registers: -# ALL: - { id: 0, class: gr64 } -# ALL: - { id: 1, class: gr64 } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1) diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir index ce3f6b91dcf..08844657e2a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir @@ -32,9 +32,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# NO_AVX512F: - { id: 1, class: vr128 } -# AVX512ALL: - { id: 1, class: vr128x } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' } +# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -60,9 +60,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64 } -# NO_AVX512F: - { id: 1, class: vr128 } -# AVX512ALL: - { id: 1, class: vr128x } +# ALL: - { id: 0, class: gr64, preferred-register: '' } +# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' } +# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: vecr } # ALL: %0 = COPY %rdi @@ -88,9 +88,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: vr128 } -# AVX512ALL: - { id: 0, class: vr128x } -# ALL: - { id: 1, class: gr64 } +# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' } +# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 @@ -118,9 +118,9 @@ alignment: 4 legalized: true regBankSelected: true registers: -# NO_AVX512F: - { id: 0, class: vr128 } -# AVX512ALL: - { id: 0, class: vr128x } -# ALL: - { id: 1, class: gr64 } +# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' } +# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' } +# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: vecr } - { id: 1, class: gpr } # ALL: %0 = COPY %xmm0 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir index b9a7e4a8cc4..ff371ad9989 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir @@ -33,12 +33,12 @@ alignment: 4 legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: gr64 } -# NO_AVX512F-NEXT: - { id: 1, class: vr256 } +# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: gr64 } -# AVX512ALL-NEXT: - { id: 1, class: vr256x } +# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -73,12 +73,12 @@ alignment: 4 legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: gr64 } -# NO_AVX512F-NEXT: - { id: 1, class: vr256 } +# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: gr64 } -# AVX512ALL-NEXT: - { id: 1, class: vr256x } +# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -113,12 +113,12 @@ alignment: 4 legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: vr256 } -# NO_AVX512F-NEXT: - { id: 1, class: gr64 } +# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: vr256x } -# AVX512ALL-NEXT: - { id: 1, class: gr64 } +# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } @@ -153,12 +153,12 @@ alignment: 4 legalized: true regBankSelected: true # NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: vr256 } -# NO_AVX512F-NEXT: - { id: 1, class: gr64 } +# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } # # AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: vr256x } -# AVX512ALL-NEXT: - { id: 1, class: gr64 } +# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir index 87978a684d4..131902d81a0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir @@ -28,8 +28,8 @@ alignment: 4 legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: gr64 } -# AVX512F-NEXT: - { id: 1, class: vr512 } +# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -54,8 +54,8 @@ alignment: 4 legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: gr64 } -# AVX512F-NEXT: - { id: 1, class: vr512 } +# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: vecr } @@ -80,8 +80,8 @@ alignment: 4 legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: vr512 } -# AVX512F-NEXT: - { id: 1, class: gr64 } +# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } @@ -106,8 +106,8 @@ alignment: 4 legalized: true regBankSelected: true # AVX512F: registers: -# AVX512F-NEXT: - { id: 0, class: vr512 } -# AVX512F-NEXT: - { id: 1, class: gr64 } +# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir index 34a77acc2d1..453557c0846 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir @@ -24,9 +24,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16 } -# ALL-NEXT: - { id: 1, class: gr16 } -# ALL-NEXT: - { id: 2, class: gr16 } +# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -55,9 +55,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -86,9 +86,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64 } -# ALL-NEXT: - { id: 1, class: gr64 } -# ALL-NEXT: - { id: 2, class: gr64 } +# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir b/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir index 5f8ab1e4f18..d3651ccd1ab 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir @@ -95,9 +95,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128 } -# CHECK-NEXT: - { id: 1, class: vr128 } -# CHECK-NEXT: - { id: 2, class: vr128 } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -121,9 +121,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128 } -# CHECK-NEXT: - { id: 1, class: vr128 } -# CHECK-NEXT: - { id: 2, class: vr128 } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -147,9 +147,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128x } -# CHECK-NEXT: - { id: 1, class: vr128x } -# CHECK-NEXT: - { id: 2, class: vr128x } +# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -173,9 +173,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128 } -# CHECK-NEXT: - { id: 1, class: vr128 } -# CHECK-NEXT: - { id: 2, class: vr128 } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -199,9 +199,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128 } -# CHECK-NEXT: - { id: 1, class: vr128 } -# CHECK-NEXT: - { id: 2, class: vr128 } +# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -225,9 +225,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128x } -# CHECK-NEXT: - { id: 1, class: vr128x } -# CHECK-NEXT: - { id: 2, class: vr128x } +# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -251,9 +251,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr128x } -# CHECK-NEXT: - { id: 1, class: vr128x } -# CHECK-NEXT: - { id: 2, class: vr128x } +# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -277,9 +277,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256 } -# CHECK-NEXT: - { id: 1, class: vr256 } -# CHECK-NEXT: - { id: 2, class: vr256 } +# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -303,9 +303,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256x } -# CHECK-NEXT: - { id: 1, class: vr256x } -# CHECK-NEXT: - { id: 2, class: vr256x } +# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -329,9 +329,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256 } -# CHECK-NEXT: - { id: 1, class: vr256 } -# CHECK-NEXT: - { id: 2, class: vr256 } +# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -355,9 +355,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256x } -# CHECK-NEXT: - { id: 1, class: vr256x } -# CHECK-NEXT: - { id: 2, class: vr256x } +# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -381,9 +381,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr256x } -# CHECK-NEXT: - { id: 1, class: vr256x } -# CHECK-NEXT: - { id: 2, class: vr256x } +# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -407,9 +407,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr512 } -# CHECK-NEXT: - { id: 1, class: vr512 } -# CHECK-NEXT: - { id: 2, class: vr512 } +# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -433,9 +433,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr512 } -# CHECK-NEXT: - { id: 1, class: vr512 } -# CHECK-NEXT: - { id: 2, class: vr512 } +# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -459,9 +459,9 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vr512 } -# CHECK-NEXT: - { id: 1, class: vr512 } -# CHECK-NEXT: - { id: 2, class: vr512 } +# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir index d60d4155e29..f77879d9300 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir @@ -32,19 +32,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128 } -# AVX512VL-NEXT: - { id: 1, class: vr128 } -# AVX512VL-NEXT: - { id: 2, class: vr128 } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -74,19 +74,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128 } -# AVX512VL-NEXT: - { id: 1, class: vr128 } -# AVX512VL-NEXT: - { id: 2, class: vr128 } +# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -116,19 +116,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -158,19 +158,19 @@ alignment: 4 legalized: true regBankSelected: true # NOVL: registers: -# NOVL-NEXT: - { id: 0, class: vr128 } -# NOVL-NEXT: - { id: 1, class: vr128 } -# NOVL-NEXT: - { id: 2, class: vr128 } +# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr128x } -# AVX512BWVL-NEXT: - { id: 1, class: vr128x } -# AVX512BWVL-NEXT: - { id: 2, class: vr128x } +# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir index fbc44997b4a..d6bde7fbb69 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir @@ -30,19 +30,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256 } -# AVX512VL-NEXT: - { id: 1, class: vr256 } -# AVX512VL-NEXT: - { id: 2, class: vr256 } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -70,19 +70,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256 } -# AVX512VL-NEXT: - { id: 1, class: vr256 } -# AVX512VL-NEXT: - { id: 2, class: vr256 } +# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -110,19 +110,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x } -# AVX512VL-NEXT: - { id: 1, class: vr256x } -# AVX512VL-NEXT: - { id: 2, class: vr256x } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -150,19 +150,19 @@ alignment: 4 legalized: true regBankSelected: true # AVX2: registers: -# AVX2-NEXT: - { id: 0, class: vr256 } -# AVX2-NEXT: - { id: 1, class: vr256 } -# AVX2-NEXT: - { id: 2, class: vr256 } +# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } +# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } # # AVX512VL: registers: -# AVX512VL-NEXT: - { id: 0, class: vr256x } -# AVX512VL-NEXT: - { id: 1, class: vr256x } -# AVX512VL-NEXT: - { id: 2, class: vr256x } +# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } # # AVX512BWVL: registers: -# AVX512BWVL-NEXT: - { id: 0, class: vr256x } -# AVX512BWVL-NEXT: - { id: 1, class: vr256x } -# AVX512BWVL-NEXT: - { id: 2, class: vr256x } +# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } +# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir index dcd05f05694..828a243b265 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir @@ -31,9 +31,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -57,9 +57,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -83,9 +83,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -109,9 +109,9 @@ alignment: 4 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: vr512 } -# ALL-NEXT: - { id: 1, class: vr512 } -# ALL-NEXT: - { id: 2, class: vr512 } +# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir index d4db6eec6d8..4768a2d9322 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir @@ -40,9 +40,9 @@ name: test_sub_i64 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64 } -# ALL-NEXT: - { id: 1, class: gr64 } -# ALL-NEXT: - { id: 2, class: gr64 } +# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -66,9 +66,9 @@ name: test_sub_i32 legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32 } -# ALL-NEXT: - { id: 1, class: gr32 } -# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -94,12 +94,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr32 } -# NO_AVX512F-NEXT: - { id: 1, class: fr32 } -# NO_AVX512F-NEXT: - { id: 2, class: fr32 } -# AVX512ALL-NEXT: - { id: 0, class: fr32x } -# AVX512ALL-NEXT: - { id: 1, class: fr32x } -# AVX512ALL-NEXT: - { id: 2, class: fr32x } +# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -128,12 +128,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr64 } -# NO_AVX512F-NEXT: - { id: 1, class: fr64 } -# NO_AVX512F-NEXT: - { id: 2, class: fr64 } -# AVX512ALL-NEXT: - { id: 0, class: fr64x } -# AVX512ALL-NEXT: - { id: 1, class: fr64x } -# AVX512ALL-NEXT: - { id: 2, class: fr64x } +# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -161,12 +161,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128 } -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } @@ -196,12 +196,12 @@ regBankSelected: true selected: false tracksRegLiveness: true # ALL: registers: -# NO_AVX512VL-NEXT: - { id: 0, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 1, class: vr128 } -# NO_AVX512VL-NEXT: - { id: 2, class: vr128 } -# AVX512VL-NEXT: - { id: 0, class: vr128x } -# AVX512VL-NEXT: - { id: 1, class: vr128x } -# AVX512VL-NEXT: - { id: 2, class: vr128x } +# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } +# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } +# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr } - { id: 1, class: vecr } diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir index 9b90543d655..4df585628dd 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir @@ -38,8 +38,8 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr8 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -64,8 +64,8 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr8 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -90,8 +90,8 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr32 } -# CHECK-NEXT: - { id: 1, class: gr16 } +# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -116,8 +116,8 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64_with_sub_8bit } -# CHECK-NEXT: - { id: 1, class: gr8 } +# CHECK-NEXT: - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -142,8 +142,8 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64 } -# CHECK-NEXT: - { id: 1, class: gr16 } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -168,8 +168,8 @@ alignment: 4 legalized: true regBankSelected: true # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gr64 } -# CHECK-NEXT: - { id: 1, class: gr32 } +# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll b/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll index 0eb17fb6c14..c1d24257525 100644 --- a/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll +++ b/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll @@ -15,5 +15,5 @@ body: ; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' } ; POST-RA: liveins: -; POST-RA-NEXT: - { reg: '%edi' } -; POST-RA-NEXT: - { reg: '%esi' } +; POST-RA-NEXT: - { reg: '%edi', virtual-reg: '' } +; POST-RA-NEXT: - { reg: '%esi', virtual-reg: '' } |
