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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-19 16:15:30 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-19 16:15:30 +0000 |
| commit | 4554e161bea9915c73f67788e1e3efd88eb92c7a (patch) | |
| tree | d327de8bb3cc7f73e9774a99fc954522999c4026 /llvm/test/CodeGen/X86 | |
| parent | c2e97249099db15523734c679bed0afafac04846 (diff) | |
| download | bcm5719-llvm-4554e161bea9915c73f67788e1e3efd88eb92c7a.tar.gz bcm5719-llvm-4554e161bea9915c73f67788e1e3efd88eb92c7a.zip | |
[DAGCombiner] Add general constant vector support to (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector
llvm-svn: 284608
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-shl.ll | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll index dc3ca5e5229..e97880369f5 100644 --- a/llvm/test/CodeGen/X86/combine-shl.ll +++ b/llvm/test/CodeGen/X86/combine-shl.ll @@ -486,24 +486,12 @@ define <4 x i32> @combine_vec_shl_ashr0(<4 x i32> %x) { define <4 x i32> @combine_vec_shl_ashr1(<4 x i32> %x) { ; SSE-LABEL: combine_vec_shl_ashr1: ; SSE: # BB#0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $8, %xmm1 -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: psrad $6, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psrad $7, %xmm1 -; SSE-NEXT: psrad $5, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] -; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_ashr1: ; AVX: # BB#0: -; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [5,6,7,8] -; AVX-NEXT: vpsravd %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq %1 = ashr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8> %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8> |

