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| author | Sanjay Patel <spatel@rotateright.com> | 2016-10-29 16:21:19 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-29 16:21:19 +0000 |
| commit | 36eeb6d6f645176ddcec07616b1f7cea6fa8b555 (patch) | |
| tree | fd9110d708da4b0f213bdde96d4900aa4fb60136 /llvm/test/CodeGen/X86 | |
| parent | e9fa95e572166f04a093f2e26a2b4937e14d4048 (diff) | |
| download | bcm5719-llvm-36eeb6d6f645176ddcec07616b1f7cea6fa8b555.tar.gz bcm5719-llvm-36eeb6d6f645176ddcec07616b1f7cea6fa8b555.zip | |
[ValueTracking] recognize more variants of smin/smax
Try harder to detect obfuscated min/max patterns: the initial pattern was added with D9352 / rL236202.
There was a bug fix for PR27137 at rL264996, but I think we can do better by folding the corresponding
smax pattern and commuted variants.
The codegen tests demonstrate the effect of ValueTracking on the backend via SelectionDAGBuilder. We
can't expose these differences minimally in IR because we don't have smin/smax intrinsics for IR.
Differential Revision: https://reviews.llvm.org/D26091
llvm-svn: 285499
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_minmax_match.ll | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/X86/vec_minmax_match.ll b/llvm/test/CodeGen/X86/vec_minmax_match.ll index 3ad631f7151..3b1176fe286 100644 --- a/llvm/test/CodeGen/X86/vec_minmax_match.ll +++ b/llvm/test/CodeGen/X86/vec_minmax_match.ll @@ -18,16 +18,12 @@ define <4 x i32> @smin_vec1(<4 x i32> %x) { ret <4 x i32> %sel } -; FIXME: These are signed min/max ops. - define <4 x i32> @smin_vec2(<4 x i32> %x) { ; CHECK-LABEL: smin_vec2: ; CHECK: # BB#0: ; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm1 -; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; CHECK-NEXT: vpcmpgtd %xmm0, %xmm2, %xmm0 -; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq ; %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -40,11 +36,8 @@ define <4 x i32> @smax_vec1(<4 x i32> %x) { ; CHECK-LABEL: smax_vec1: ; CHECK: # BB#0: ; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm2 -; CHECK-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; CHECK-NEXT: vpcmpgtd %xmm0, %xmm3, %xmm0 ; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vpor %xmm2, %xmm0, %xmm0 +; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq ; %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -57,10 +50,8 @@ define <4 x i32> @smax_vec2(<4 x i32> %x) { ; CHECK-LABEL: smax_vec2: ; CHECK: # BB#0: ; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm1 -; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; CHECK-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm0 -; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq ; %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> |
