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| author | Amjad Aboud <amjad.aboud@intel.com> | 2017-04-03 20:28:45 +0000 |
|---|---|---|
| committer | Amjad Aboud <amjad.aboud@intel.com> | 2017-04-03 20:28:45 +0000 |
| commit | 0389f62879fc9162fae12e57b93ae3565c915356 (patch) | |
| tree | f3cf5519ed3b9533f9d72177a870ee1e7b6f22ed /llvm/test/CodeGen/X86 | |
| parent | 27b71e5b1b40a908f970b11ac6a1b7730ab1ed36 (diff) | |
| download | bcm5719-llvm-0389f62879fc9162fae12e57b93ae3565c915356.tar.gz bcm5719-llvm-0389f62879fc9162fae12e57b93ae3565c915356.zip | |
x86 interrupt calling convention: re-align stack pointer on 64-bit if an error code was pushed
The x86_64 ABI requires that the stack is 16 byte aligned on function calls. Thus, the 8-byte error code, which is pushed by the CPU for certain exceptions, leads to a misaligned stack. This results in bugs such as Bug 26413, where misaligned movaps instructions are generated.
This commit fixes the misalignment by adjusting the stack pointer in these cases. The adjustment is done at the beginning of the prologue generation by subtracting another 8 bytes from the stack pointer. These additional bytes are popped again in the function epilogue.
Fixes Bug 26413
Patch by Philipp Oppermann.
Differential Revision: https://reviews.llvm.org/D30049
llvm-svn: 299383
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-64-intrcc.ll | 17 |
2 files changed, 12 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll b/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll index 0bb4e47adf0..ab84088c344 100644 --- a/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll +++ b/llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll @@ -9,10 +9,11 @@ define x86_intrcc void @test_isr_sse_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) { ; CHECK-LABEL: test_isr_sse_clobbers: ; CHECK: # BB#0: + ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: cld ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP - ; CHECK-NEXT: addq $8, %rsp + ; CHECK-NEXT: addq $16, %rsp ; CHECK-NEXT: iretq call void asm sideeffect "", "~{xmm0},~{xmm6}"() ret void diff --git a/llvm/test/CodeGen/X86/x86-64-intrcc.ll b/llvm/test/CodeGen/X86/x86-64-intrcc.ll index 2bcf3cde478..c8bc9e716ce 100644 --- a/llvm/test/CodeGen/X86/x86-64-intrcc.ll +++ b/llvm/test/CodeGen/X86/x86-64-intrcc.ll @@ -30,22 +30,24 @@ define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) { define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) { ; CHECK-LABEL: test_isr_ecode ; CHECK: pushq %rax + ; CHECK: pushq %rax ; CHECK: pushq %rcx - ; CHECK: movq 16(%rsp), %rax - ; CHECK: movq 40(%rsp), %rcx + ; CHECK: movq 24(%rsp), %rax + ; CHECK: movq 48(%rsp), %rcx ; CHECK: popq %rcx ; CHECK: popq %rax - ; CHECK: addq $8, %rsp + ; CHECK: addq $16, %rsp ; CHECK: iretq ; CHECK0-LABEL: test_isr_ecode ; CHECK0: pushq %rax + ; CHECK0: pushq %rax ; CHECK0: pushq %rcx - ; CHECK0: movq 16(%rsp), %rax - ; CHECK0: leaq 24(%rsp), %rcx + ; CHECK0: movq 24(%rsp), %rax + ; CHECK0: leaq 32(%rsp), %rcx ; CHECK0: movq 16(%rcx), %rcx ; CHECK0: popq %rcx ; CHECK0: popq %rax - ; CHECK0: addq $8, %rsp + ; CHECK0: addq $16, %rsp ; CHECK0: iretq %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2 %flags = load i64, i64* %pflags, align 4 @@ -58,6 +60,7 @@ define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 % call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"() ; CHECK-LABEL: test_isr_clobbers ; CHECK-SSE-NEXT: pushq %rax + ; CHECK-SSE-NEXT: pushq %rax ; CHECK-SSE-NEXT; pushq %r11 ; CHECK-SSE-NEXT: pushq %rbp ; CHECK-SSE-NEXT: pushq %rbx @@ -80,7 +83,7 @@ define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 % ; CHECK0-SSE-NEXT: popq %rbp ; CHECK0-SSE-NEXT: popq %r11 ; CHECK0-SSE-NEXT: popq %rax - ; CHECK0-SSE-NEXT: addq $8, %rsp + ; CHECK0-SSE-NEXT: addq $16, %rsp ; CHECK0-SSE-NEXT: iretq ret void } |
