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| author | Dan Gohman <gohman@apple.com> | 2008-08-06 18:27:21 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-06 18:27:21 +0000 |
| commit | 91c2c432c0944653dde801805cfd5a101dc7c063 (patch) | |
| tree | 1c79743be7f8f430d1de6cdd9e620c0ce3d957c9 /llvm/test/CodeGen/X86/zext-inreg-0.ll | |
| parent | ac22cfcae954c9b1f1893ef62487fe50c221aa1b (diff) | |
| download | bcm5719-llvm-91c2c432c0944653dde801805cfd5a101dc7c063.tar.gz bcm5719-llvm-91c2c432c0944653dde801805cfd5a101dc7c063.zip | |
Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.
llvm-svn: 54418
Diffstat (limited to 'llvm/test/CodeGen/X86/zext-inreg-0.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/zext-inreg-0.ll | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/zext-inreg-0.ll b/llvm/test/CodeGen/X86/zext-inreg-0.ll index 62c651c8350..1a734642d03 100644 --- a/llvm/test/CodeGen/X86/zext-inreg-0.ll +++ b/llvm/test/CodeGen/X86/zext-inreg-0.ll @@ -8,11 +8,26 @@ ; These should use movzbl instead of 'and 255'. ; This related to not having a ZERO_EXTEND_REG opcode. +define i32 @a(i32 %d) nounwind { + %e = add i32 %d, 1 + %retval = and i32 %e, 255 + ret i32 %retval +} +define i32 @b(float %d) nounwind { + %tmp12 = fptoui float %d to i8 + %retval = zext i8 %tmp12 to i32 + ret i32 %retval +} define i32 @c(i32 %d) nounwind { %e = add i32 %d, 1 %retval = and i32 %e, 65535 ret i32 %retval } +define i64 @d(i64 %d) nounwind { + %e = add i64 %d, 1 + %retval = and i64 %e, 255 + ret i64 %retval +} define i64 @e(i64 %d) nounwind { %e = add i64 %d, 1 %retval = and i64 %e, 65535 |
