[X86][SSE] Regenerate vshift tests

llvm-svn: 277278

1 files changed, 75 insertions, 14 deletions

diff --git a/llvm/test/CodeGen/X86/vshift-3.ll b/llvm/test/CodeGen/X86/vshift-3.ll
index f368029e4b4..c59dacec6e3 100644
--- a/llvm/test/CodeGen/X86/vshift-3.ll
+++ b/llvm/test/CodeGen/X86/vshift-3.ll
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same.
@@ -6,28 +8,65 @@
 ; Note that x86 does have ashr
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+; X32-LABEL: shift1a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; X32-NEXT:    psrad $31, %xmm0
+; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X32-NEXT:    movdqa %xmm1, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; X64-NEXT:    psrad $31, %xmm0
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X64-NEXT:    movdqa %xmm1, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1a:
-; CHECK: psrad $31
   %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %ashr, <2 x i64>* %dst
   ret void
 }
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+; X32-LABEL: shift2a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psrad $5, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psrad $5, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2a:
-; CHECK: psrad	$5
   %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %ashr, <4 x i32>* %dst
   ret void
 }
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+; X32-LABEL: shift2b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    psrad %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %esi, %xmm1
+; X64-NEXT:    psrad %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2b:
-; CHECK: movd
-; CHECK: psrad
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
   %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
@@ -38,20 +77,42 @@ entry:
 }
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+; X32-LABEL: shift3a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psraw $5, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psraw $5, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3a:
-; CHECK: psraw	$5
   %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %ashr, <8 x i16>* %dst
   ret void
 }
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+; X32-LABEL: shift3b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movd %ecx, %xmm1
+; X32-NEXT:    psraw %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movzwl %si, %eax
+; X64-NEXT:    movd %eax, %xmm1
+; X64-NEXT:    psraw %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3b:
-; CHECK: movzwl
-; CHECK: movd
-; CHECK: psraw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
   %2 = insertelement <8 x i16> %1, i16 %amt, i32 2