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author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
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committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/X86/vector-variable-idx2.ll | |
parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-variable-idx2.ll')
-rw-r--r-- | llvm/test/CodeGen/X86/vector-variable-idx2.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/vector-variable-idx2.ll b/llvm/test/CodeGen/X86/vector-variable-idx2.ll index 6e8ae2e42c9..df65257bac7 100644 --- a/llvm/test/CodeGen/X86/vector-variable-idx2.ll +++ b/llvm/test/CodeGen/X86/vector-variable-idx2.ll @@ -8,8 +8,8 @@ define i64 @__builtin_ia32_vec_ext_v2di(<2 x i64> %a, i32 %i) nounwind { %2 = alloca i32, align 4 store <2 x i64> %a, <2 x i64>* %1, align 16 store i32 %i, i32* %2, align 4 - %3 = load <2 x i64>* %1, align 16 - %4 = load i32* %2, align 4 + %3 = load <2 x i64>, <2 x i64>* %1, align 16 + %4 = load i32, i32* %2, align 4 %5 = extractelement <2 x i64> %3, i32 %4 ret i64 %5 } @@ -19,8 +19,8 @@ define <2 x i64> @__builtin_ia32_vec_int_v2di(<2 x i64> %a, i32 %i) nounwind { %2 = alloca i32, align 4 store <2 x i64> %a, <2 x i64>* %1, align 16 store i32 %i, i32* %2, align 4 - %3 = load <2 x i64>* %1, align 16 - %4 = load i32* %2, align 4 + %3 = load <2 x i64>, <2 x i64>* %1, align 16 + %4 = load i32, i32* %2, align 4 %5 = insertelement <2 x i64> %3, i64 1, i32 %4 ret <2 x i64> %5 } |