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| author | Quentin Colombet <qcolombet@apple.com> | 2018-02-17 03:05:33 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2018-02-17 03:05:33 +0000 |
| commit | 48abac82b808315d387185bb2e44688add679073 (patch) | |
| tree | c823fab58ad69d0fdcce742bdc1b037d804dfd59 /llvm/test/CodeGen/X86/vector-trunc-math.ll | |
| parent | a1d6107b14b3ceaf5a34a00c1326775ac72e353f (diff) | |
| download | bcm5719-llvm-48abac82b808315d387185bb2e44688add679073.tar.gz bcm5719-llvm-48abac82b808315d387185bb2e44688add679073.zip | |
Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
This reverts commit r323991.
This commit breaks target that don't model all the register constraints
in TableGen. So far the workaround was to set the
hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the
cases.
For instance, when mutating an instruction (like in the lowering of
COPYs) the isRenamable flag is not properly updated. The same problem
will happen when attaching machine operand from one instruction to
another.
Geoff Berry is working on a fix in https://reviews.llvm.org/D43042.
llvm-svn: 325421
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-trunc-math.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-trunc-math.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/vector-trunc-math.ll b/llvm/test/CodeGen/X86/vector-trunc-math.ll index f0a5449585c..80629a388b4 100644 --- a/llvm/test/CodeGen/X86/vector-trunc-math.ll +++ b/llvm/test/CodeGen/X86/vector-trunc-math.ll @@ -5511,7 +5511,7 @@ define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwi ; SSE-LABEL: mul_add_const_v4i64_v4i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,1,1,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3] |
