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| author | Craig Topper <craig.topper@gmail.com> | 2017-01-14 07:50:52 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-01-14 07:50:52 +0000 |
| commit | 63e2cd6caa14e1ed5b383c4f68a7f913a2c834eb (patch) | |
| tree | 77a421301749186159d75d4716bc9869a4b6cb0c /llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll | |
| parent | 09b7e0f01d0505b2ba1e3340486685c0393f2b55 (diff) | |
| download | bcm5719-llvm-63e2cd6caa14e1ed5b383c4f68a7f913a2c834eb.tar.gz bcm5719-llvm-63e2cd6caa14e1ed5b383c4f68a7f913a2c834eb.zip | |
[AVX-512] Teach two address instruction pass to replace masked move instructions with blendm instructions when its beneficial.
Isel now selects masked move instructions for vselect instead of blendm. But sometimes it beneficial to register allocation to remove the tied register constraint by using blendm instructions.
This also picks up cases where the masked move was created due to a masked load intrinsic.
Differential Revision: https://reviews.llvm.org/D28454
llvm-svn: 292005
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll index 4876aa1526a..390ab16699d 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll @@ -1036,8 +1036,7 @@ define <32 x i8> @shuffle_v32i8_00_33_02_35_04_37_06_39_08_41_10_43_12_45_14_47_ ; AVX512VL: # BB#0: ; AVX512VL-NEXT: movl $-1431655766, %eax # imm = 0xAAAAAAAA ; AVX512VL-NEXT: kmovd %eax, %k1 -; AVX512VL-NEXT: vmovdqu8 %ymm0, %ymm1 {%k1} -; AVX512VL-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VL-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1} ; AVX512VL-NEXT: retq %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 0, i32 33, i32 2, i32 35, i32 4, i32 37, i32 6, i32 39, i32 8, i32 41, i32 10, i32 43, i32 12, i32 45, i32 14, i32 47, i32 16, i32 49, i32 18, i32 51, i32 20, i32 53, i32 22, i32 55, i32 24, i32 57, i32 26, i32 59, i32 28, i32 61, i32 30, i32 63> ret <32 x i8> %shuffle |
