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| author | Craig Topper <craig.topper@intel.com> | 2018-01-08 06:53:54 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-08 06:53:54 +0000 |
| commit | f090e8a89a9b58e462422ba730310bccfd052ee4 (patch) | |
| tree | da18c332740a6aa4c54d4132db4b22cb305bb293 /llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | |
| parent | a2018e799a716aaaef9ced091e79994255e0b161 (diff) | |
| download | bcm5719-llvm-f090e8a89a9b58e462422ba730310bccfd052ee4.tar.gz bcm5719-llvm-f090e8a89a9b58e462422ba730310bccfd052ee4.zip | |
[X86] Replace CVT2MASK ISD opcode with PCMPGTM compared to zero.
CVT2MASK is just checking the sign bit which can be represented with a comparison with zero.
llvm-svn: 321985
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-shift-ashr-512.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shift-ashr-512.ll b/llvm/test/CodeGen/X86/vector-shift-ashr-512.ll index 77fb34a95a3..1d5a47b6df9 100644 --- a/llvm/test/CodeGen/X86/vector-shift-ashr-512.ll +++ b/llvm/test/CodeGen/X86/vector-shift-ashr-512.ll @@ -463,8 +463,7 @@ define <64 x i8> @ashr_const7_v64i8(<64 x i8> %a) { ; ; AVX512BW-LABEL: ashr_const7_v64i8: ; AVX512BW: # %bb.0: -; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX512BW-NEXT: vpcmpgtb %zmm0, %zmm1, %k0 +; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 ; AVX512BW-NEXT: retq %res = ashr <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> |
