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| author | Craig Topper <craig.topper@intel.com> | 2019-10-28 11:10:49 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-10-28 11:27:01 -0700 |
| commit | 3da269a2489f156462fca74311842d761151393f (patch) | |
| tree | 9dd51543e74026276ff668170942518e38ff70cc /llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | |
| parent | 8aa0a785c423ebea84876b71f7b735bee96a0292 (diff) | |
| download | bcm5719-llvm-3da269a2489f156462fca74311842d761151393f.tar.gz bcm5719-llvm-3da269a2489f156462fca74311842d761151393f.zip | |
[X86] Add a DAG combine to turn (and (bitcast (vXi1 (concat_vectors (vYi1 setcc), undef,))), C) into (bitcast (vXi1 (concat_vectors (vYi1 setcc), zero,)))
The legalization of v2i1->i2 or v4i1->i4 bitcasts followed by a setcc can create an and after the bitcast. If we're lucky enough that the input to the bitcast is a concat_vectors where the first operand is a setcc that can natively 0 all the upper bits of ak-register, then we should replace the other operands of the concat_vectors with zero in order to remove the AND.
With the AND removed we might be able to use a kortest on the result.
Differential Revision: https://reviews.llvm.org/D69205
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-reduce-and-bool.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll b/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll index 49add302bf4..37bd440e7e7 100644 --- a/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll +++ b/llvm/test/CodeGen/X86/vector-reduce-and-bool.ll @@ -55,7 +55,6 @@ define i1 @trunc_v2i64_v2i1(<2 x i64>) { ; AVX512VL-NEXT: vpsllq $63, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmq %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: andb $3, %al ; AVX512VL-NEXT: cmpb $3, %al ; AVX512VL-NEXT: sete %al ; AVX512VL-NEXT: retq @@ -108,7 +107,6 @@ define i1 @trunc_v4i32_v4i1(<4 x i32>) { ; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: andb $15, %al ; AVX512VL-NEXT: cmpb $15, %al ; AVX512VL-NEXT: sete %al ; AVX512VL-NEXT: retq @@ -259,7 +257,6 @@ define i1 @trunc_v4i64_v4i1(<4 x i64>) { ; AVX512VL-NEXT: vpsllq $63, %ymm0, %ymm0 ; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: andb $15, %al ; AVX512VL-NEXT: cmpb $15, %al ; AVX512VL-NEXT: sete %al ; AVX512VL-NEXT: vzeroupper @@ -943,7 +940,6 @@ define i1 @icmp_v2i64_v2i1(<2 x i64>) { ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vptestnmq %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: andb $3, %al ; AVX512VL-NEXT: cmpb $3, %al ; AVX512VL-NEXT: sete %al ; AVX512VL-NEXT: retq @@ -997,7 +993,6 @@ define i1 @icmp_v4i32_v4i1(<4 x i32>) { ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vptestnmd %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: andb $15, %al ; AVX512VL-NEXT: cmpb $15, %al ; AVX512VL-NEXT: sete %al ; AVX512VL-NEXT: retq @@ -1198,7 +1193,6 @@ define i1 @icmp_v4i64_v4i1(<4 x i64>) { ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vptestnmq %ymm0, %ymm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: andb $15, %al ; AVX512VL-NEXT: cmpb $15, %al ; AVX512VL-NEXT: sete %al ; AVX512VL-NEXT: vzeroupper |
