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| author | Chandler Carruth <chandlerc@gmail.com> | 2014-09-04 09:26:30 +0000 |
|---|---|---|
| committer | Chandler Carruth <chandlerc@gmail.com> | 2014-09-04 09:26:30 +0000 |
| commit | 2e5134f8f4b2656c2e6cf2f7d7851415db041cf7 (patch) | |
| tree | 5b5046c1ee1a198c4180d4d9a26073008cb56a82 /llvm/test/CodeGen/X86/vec_set-3.ll | |
| parent | 94ad0bf10d5b9f2875485e8c7c70d8c2dc1d577c (diff) | |
| download | bcm5719-llvm-2e5134f8f4b2656c2e6cf2f7d7851415db041cf7.tar.gz bcm5719-llvm-2e5134f8f4b2656c2e6cf2f7d7851415db041cf7.zip | |
[x86] Teach the new v4i32 shuffle lowering some more tricks to recognize
vzext patterns and insert-element patterns that for SSE4 have dedicated
instructions.
With this we can enable the experimental mode in a regression test that
happens to cover some of the past set of issues. You can see that the
new logic does significantly better here on the floating point cases.
A follow-up to this change and the previous ones will hoist the logic
into helpers so it can be shared across element type sizes as in this
particular case it generalizes cleanly.
llvm-svn: 217136
Diffstat (limited to 'llvm/test/CodeGen/X86/vec_set-3.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_set-3.ll | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vec_set-3.ll b/llvm/test/CodeGen/X86/vec_set-3.ll index bdd85213885..9823963d61b 100644 --- a/llvm/test/CodeGen/X86/vec_set-3.ll +++ b/llvm/test/CodeGen/X86/vec_set-3.ll @@ -1,10 +1,15 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-EXP define <4 x float> @test(float %a) { ; CHECK-LABEL: test: ; CHECK: movss {{.*}}, %xmm0 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1] ; CHECK-NEXT: retl +; +; CHECK-EXP-LABEL: test: +; CHECK-EXP: insertps $285, {{.*}}, %xmm0 +; CHECK-EXP-NEXT: retl entry: %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1 @@ -18,6 +23,11 @@ define <2 x i64> @test2(i32 %a) { ; CHECK: movd {{.*}}, %xmm0 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,0,1] ; CHECK-NEXT: retl +; +; CHECK-EXP-LABEL: test2: +; CHECK-EXP: movd {{.*}}, %xmm0 +; CHECK-EXP-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,0,1] +; CHECK-EXP-NEXT: retl entry: %tmp7 = insertelement <4 x i32> zeroinitializer, i32 %a, i32 2 @@ -32,6 +42,10 @@ define <4 x float> @test3(<4 x float> %A) { ; CHECK-NEXT: movss %xmm0, %[[X1]] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = [[X1]][1,0,1,1] ; CHECK-NEXT: retl +; +; CHECK-EXP-LABEL: test3: +; CHECK-EXP: insertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero +; CHECK-EXP-NEXT: retl %tmp0 = extractelement <4 x float> %A, i32 0 %tmp1 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef >, float %tmp0, i32 1 |
