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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2015-12-07 14:33:34 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2015-12-07 14:33:34 +0000 |
| commit | 291fe0159f1869619718b33b7ac6435935d9d63b (patch) | |
| tree | 461b7d328cf95dc518549d0503cc366ca2db595f /llvm/test/CodeGen/X86/vec_fabs.ll | |
| parent | e9b3fb86034fb4a444f4ad81532a0cde63ac9cb3 (diff) | |
| download | bcm5719-llvm-291fe0159f1869619718b33b7ac6435935d9d63b.tar.gz bcm5719-llvm-291fe0159f1869619718b33b7ac6435935d9d63b.zip | |
VX-512: Fixed a bug in FP logic operation lowering
FP logic instructions are supported in DQ extension on AVX-512 target.
I use integer operations instead.
Added tests.
I also enabled FABS in this patch in order to check ANDPS.
The operations are FOR, FXOR, FAND, FANDN.
The instructions, that supported for 512-bit vector under DQ are:
VORPS/PD, VXORPS/PD, VANDPS/PD, FANDNPS/PD.
Differential Revision: http://reviews.llvm.org/D15110
llvm-svn: 254913
Diffstat (limited to 'llvm/test/CodeGen/X86/vec_fabs.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_fabs.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll index 960b5f27cf5..54f33b2bd22 100644 --- a/llvm/test/CodeGen/X86/vec_fabs.ll +++ b/llvm/test/CodeGen/X86/vec_fabs.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s - +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s define <2 x double> @fabs_v2f64(<2 x double> %p) { |
