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| author | Craig Topper <craig.topper@intel.com> | 2018-02-16 18:51:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-16 18:51:09 +0000 |
| commit | de565fc73e9047a3044e8680c88aa6a3530a16e6 (patch) | |
| tree | cdd81832ecc23ade8fad9d77172543e883008389 /llvm/test/CodeGen/X86/test-vs-bittest.ll | |
| parent | 3d1f4b954d888a30e2aa09848b0c696dfa20b787 (diff) | |
| download | bcm5719-llvm-de565fc73e9047a3044e8680c88aa6a3530a16e6.tar.gz bcm5719-llvm-de565fc73e9047a3044e8680c88aa6a3530a16e6.zip | |
[X86] Only reorder srl/and on last DAG combiner run
This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST.
We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering.
Differential Revision: https://reviews.llvm.org/D43201
llvm-svn: 325371
Diffstat (limited to 'llvm/test/CodeGen/X86/test-vs-bittest.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/test-vs-bittest.ll | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/test-vs-bittest.ll b/llvm/test/CodeGen/X86/test-vs-bittest.ll index 44f77e8b7ce..d20a7579092 100644 --- a/llvm/test/CodeGen/X86/test-vs-bittest.ll +++ b/llvm/test/CodeGen/X86/test-vs-bittest.ll @@ -6,8 +6,8 @@ define void @test64(i64 inreg %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: btl $11, %edi -; CHECK-NEXT: jb .LBB0_2 +; CHECK-NEXT: testl $2048, %edi # imm = 0x800 +; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: # %bb.1: # %yes ; CHECK-NEXT: callq bar ; CHECK-NEXT: .LBB0_2: # %no @@ -47,6 +47,11 @@ no: ret void } +; This test is identical to test64 above with only the destination of the br +; reversed. This somehow causes the two functions to get slightly different +; initial IR. One has an extra invert of the setcc. This previous caused one +; the functions to use a BT while the other used a TEST due to another DAG +; combine messing with an expected canonical form. define void @test64_2(i64 inreg %x) { ; CHECK-LABEL: test64_2: ; CHECK: # %bb.0: @@ -190,8 +195,8 @@ define void @test32(i32 inreg %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: btl $11, %edi -; CHECK-NEXT: jb .LBB8_2 +; CHECK-NEXT: testl $2048, %edi # imm = 0x800 +; CHECK-NEXT: jne .LBB8_2 ; CHECK-NEXT: # %bb.1: # %yes ; CHECK-NEXT: callq bar ; CHECK-NEXT: .LBB8_2: # %no @@ -282,8 +287,8 @@ define void @test16(i16 inreg %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: btl $11, %edi -; CHECK-NEXT: jb .LBB12_2 +; CHECK-NEXT: testl $2048, %edi # imm = 0x800 +; CHECK-NEXT: jne .LBB12_2 ; CHECK-NEXT: # %bb.1: # %yes ; CHECK-NEXT: callq bar ; CHECK-NEXT: .LBB12_2: # %no |
