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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/X86/shl-i64.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/X86/shl-i64.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/shl-i64.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/shl-i64.ll b/llvm/test/CodeGen/X86/shl-i64.ll index 073b35bf7c1..849912cc12e 100644 --- a/llvm/test/CodeGen/X86/shl-i64.ll +++ b/llvm/test/CodeGen/X86/shl-i64.ll @@ -7,9 +7,9 @@ define void @test_cl(<4 x i64>* %dst, <4 x i64>* %src, i32 %idx) { entry: %arrayidx = getelementptr inbounds <4 x i64>, <4 x i64> * %src, i32 %idx - %0 = load <4 x i64> * %arrayidx, align 32 + %0 = load <4 x i64> , <4 x i64> * %arrayidx, align 32 %arrayidx1 = getelementptr inbounds <4 x i64>, <4 x i64> * %dst, i32 %idx - %1 = load <4 x i64> * %arrayidx1, align 32 + %1 = load <4 x i64> , <4 x i64> * %arrayidx1, align 32 %2 = extractelement <4 x i64> %1, i32 0 %and = and i64 %2, 63 %3 = insertelement <4 x i64> undef, i64 %and, i32 0 |
