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| author | Sanjay Patel <spatel@rotateright.com> | 2017-03-12 18:28:48 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2017-03-12 18:28:48 +0000 |
| commit | f06b963a2b4550128be28ca119c88486a6b3e478 (patch) | |
| tree | 0e825356cca58c9758126a11d109e3a3ab9ff16a /llvm/test/CodeGen/X86/setcc.ll | |
| parent | d5bd3a1e6abf1996dc883335a3957526d1186117 (diff) | |
| download | bcm5719-llvm-f06b963a2b4550128be28ca119c88486a6b3e478.tar.gz bcm5719-llvm-f06b963a2b4550128be28ca119c88486a6b3e478.zip | |
[x86] don't blindly transform SETB into SBB
I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently.
This happens because we were transforming any 'setb' - even when we only wanted a single-bit result.
This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it
is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that
existing behavior in this patch.
Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files
where this transform still fires.
The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register
stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate
issue.
Differential Revision: https://reviews.llvm.org/D30611
llvm-svn: 297586
Diffstat (limited to 'llvm/test/CodeGen/X86/setcc.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/setcc.ll | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/setcc.ll b/llvm/test/CodeGen/X86/setcc.ll index 1b8f1ce4c9e..fab4f413725 100644 --- a/llvm/test/CodeGen/X86/setcc.ll +++ b/llvm/test/CodeGen/X86/setcc.ll @@ -21,9 +21,10 @@ define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp { define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp { ; CHECK-LABEL: t2: ; CHECK: ## BB#0: +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl $26, %edi -; CHECK-NEXT: sbbl %eax, %eax -; CHECK-NEXT: andl $32, %eax +; CHECK-NEXT: setb %al +; CHECK-NEXT: shll $5, %eax ; CHECK-NEXT: retq %t0 = icmp ult i16 %x, 26 %if = select i1 %t0, i16 32, i16 0 @@ -33,9 +34,10 @@ define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp { define i64 @t3(i64 %x) nounwind readnone ssp { ; CHECK-LABEL: t3: ; CHECK: ## BB#0: +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpq $18, %rdi -; CHECK-NEXT: sbbq %rax, %rax -; CHECK-NEXT: andl $64, %eax +; CHECK-NEXT: setb %al +; CHECK-NEXT: shlq $6, %rax ; CHECK-NEXT: retq %t0 = icmp ult i64 %x, 18 %if = select i1 %t0, i64 64, i64 0 |
