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| author | Michael Kuperstein <mkuper@google.com> | 2016-07-07 22:50:23 +0000 |
|---|---|---|
| committer | Michael Kuperstein <mkuper@google.com> | 2016-07-07 22:50:23 +0000 |
| commit | 3e3652aef22e2b19e88d48bc9a19834745b910d1 (patch) | |
| tree | 71f0b93019945f8bb8882c36e8fec0d8a3d7754e /llvm/test/CodeGen/X86/setcc.ll | |
| parent | 0fdffd37095b5c5c405518d3fa651315a29a7dc5 (diff) | |
| download | bcm5719-llvm-3e3652aef22e2b19e88d48bc9a19834745b910d1.tar.gz bcm5719-llvm-3e3652aef22e2b19e88d48bc9a19834745b910d1.zip | |
Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setcc
xorl + setcc is generally the preferred sequence due to the partial register
stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller.
This fixes PR28146.
The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD)
which was not appreciated by fast regalloc on 32-bit.
llvm-svn: 274802
Diffstat (limited to 'llvm/test/CodeGen/X86/setcc.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/setcc.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/setcc.ll b/llvm/test/CodeGen/X86/setcc.ll index d5874344fd1..eabcda4e075 100644 --- a/llvm/test/CodeGen/X86/setcc.ll +++ b/llvm/test/CodeGen/X86/setcc.ll @@ -7,8 +7,8 @@ define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp { entry: ; CHECK-LABEL: t1: +; CHECK: xorl %eax, %eax ; CHECK: seta %al -; CHECK: movzbl %al, %eax ; CHECK: shll $5, %eax %0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1] %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1] |
