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authorSanjay Patel <spatel@rotateright.com>2017-08-06 16:27:07 +0000
committerSanjay Patel <spatel@rotateright.com>2017-08-06 16:27:07 +0000
commita923c2ee95a4b3b6d43a850789ba56c6aa249b3c (patch)
treebe69b92b4063e1ba19c60cf82a2611f084c21a2f /llvm/test/CodeGen/X86/select_const.ll
parenta9b5bbac789a69322ec62011bcb8e8462a097e59 (diff)
downloadbcm5719-llvm-a923c2ee95a4b3b6d43a850789ba56c6aa249b3c.tar.gz
bcm5719-llvm-a923c2ee95a4b3b6d43a850789ba56c6aa249b3c.zip
[x86] use more shift or LEA for select-of-constants
We can convert any select-of-constants to math ops: http://rise4fun.com/Alive/d7d For this patch, I'm enhancing an existing x86 transform that uses fake multiplies (they always become shl/lea) to avoid cmov or branching. The current code misses cases where we have a negative constant and a positive constant, so this is just trying to plug that hole. The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start with a select in IR, create a select DAG node, convert it into a sext, convert it back into a select, and then lower it to sext machine code. Some notes about the test diffs: 1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR. 2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. I think we could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on a different reg? That's a post-DAG problem though. 3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if that's a regression, but I think those would always be nearly equivalent. 4. pr22338.ll and sext-i1.ll - These tests have undef operands, so I don't think we actually care about these diffs. 5. sbb.ll - This shows a win for what I think is a common case: choose -1 or 0. 6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again. 7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops. Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass. Differential Revision: https://reviews.llvm.org/D35340 llvm-svn: 310208
Diffstat (limited to 'llvm/test/CodeGen/X86/select_const.ll')
-rw-r--r--llvm/test/CodeGen/X86/select_const.ll61
1 files changed, 27 insertions, 34 deletions
diff --git a/llvm/test/CodeGen/X86/select_const.ll b/llvm/test/CodeGen/X86/select_const.ll
index 0eb9bf46ffd..105abc1161b 100644
--- a/llvm/test/CodeGen/X86/select_const.ll
+++ b/llvm/test/CodeGen/X86/select_const.ll
@@ -211,10 +211,9 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) {
define i32 @select_lea_2(i1 zeroext %cond) {
; CHECK-LABEL: select_lea_2:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movl $-1, %ecx
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: cmovnel %ecx, %eax
+; CHECK-NEXT: xorb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: leal -1(%rax,%rax), %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 -1, i32 1
ret i32 %sel
@@ -223,10 +222,9 @@ define i32 @select_lea_2(i1 zeroext %cond) {
define i64 @select_lea_3(i1 zeroext %cond) {
; CHECK-LABEL: select_lea_3:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movl $1, %ecx
-; CHECK-NEXT: movq $-2, %rax
-; CHECK-NEXT: cmoveq %rcx, %rax
+; CHECK-NEXT: xorb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: leaq -2(%rax,%rax,2), %rax
; CHECK-NEXT: retq
%sel = select i1 %cond, i64 -2, i64 1
ret i64 %sel
@@ -235,10 +233,9 @@ define i64 @select_lea_3(i1 zeroext %cond) {
define i32 @select_lea_5(i1 zeroext %cond) {
; CHECK-LABEL: select_lea_5:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movl $-2, %ecx
-; CHECK-NEXT: movl $3, %eax
-; CHECK-NEXT: cmovnel %ecx, %eax
+; CHECK-NEXT: xorb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: leal -2(%rax,%rax,4), %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 -2, i32 3
ret i32 %sel
@@ -247,10 +244,9 @@ define i32 @select_lea_5(i1 zeroext %cond) {
define i64 @select_lea_9(i1 zeroext %cond) {
; CHECK-LABEL: select_lea_9:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movl $2, %ecx
-; CHECK-NEXT: movq $-7, %rax
-; CHECK-NEXT: cmoveq %rcx, %rax
+; CHECK-NEXT: xorb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: leaq -7(%rax,%rax,8), %rax
; CHECK-NEXT: retq
%sel = select i1 %cond, i64 -7, i64 2
ret i64 %sel
@@ -263,12 +259,9 @@ define i64 @select_lea_9(i1 zeroext %cond) {
define i8 @select_pow2_diff(i1 zeroext %cond) {
; CHECK-LABEL: select_pow2_diff:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movb $19, %al
-; CHECK-NEXT: jne .LBB22_2
-; CHECK-NEXT: # BB#1:
-; CHECK-NEXT: movb $3, %al
-; CHECK-NEXT: .LBB22_2:
+; CHECK-NEXT: shlb $4, %dil
+; CHECK-NEXT: orb $3, %dil
+; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i8 19, i8 3
ret i8 %sel
@@ -277,10 +270,11 @@ define i8 @select_pow2_diff(i1 zeroext %cond) {
define i16 @select_pow2_diff_invert(i1 zeroext %cond) {
; CHECK-LABEL: select_pow2_diff_invert:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movw $7, %cx
-; CHECK-NEXT: movw $71, %ax
-; CHECK-NEXT: cmovnew %cx, %ax
+; CHECK-NEXT: xorb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: shll $6, %eax
+; CHECK-NEXT: orl $7, %eax
+; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; CHECK-NEXT: retq
%sel = select i1 %cond, i16 7, i16 71
ret i16 %sel
@@ -289,10 +283,9 @@ define i16 @select_pow2_diff_invert(i1 zeroext %cond) {
define i32 @select_pow2_diff_neg(i1 zeroext %cond) {
; CHECK-LABEL: select_pow2_diff_neg:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movl $-9, %ecx
-; CHECK-NEXT: movl $-25, %eax
-; CHECK-NEXT: cmovnel %ecx, %eax
+; CHECK-NEXT: shlb $4, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: orl $-25, %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 -9, i32 -25
ret i32 %sel
@@ -301,10 +294,10 @@ define i32 @select_pow2_diff_neg(i1 zeroext %cond) {
define i64 @select_pow2_diff_neg_invert(i1 zeroext %cond) {
; CHECK-LABEL: select_pow2_diff_neg_invert:
; CHECK: # BB#0:
-; CHECK-NEXT: testb %dil, %dil
-; CHECK-NEXT: movl $29, %ecx
-; CHECK-NEXT: movq $-99, %rax
-; CHECK-NEXT: cmoveq %rcx, %rax
+; CHECK-NEXT: xorb $1, %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: shlq $7, %rax
+; CHECK-NEXT: addq $-99, %rax
; CHECK-NEXT: retq
%sel = select i1 %cond, i64 -99, i64 29
ret i64 %sel
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