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| author | Nirav Dave <niravd@google.com> | 2018-03-09 20:57:42 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2018-03-09 20:57:42 +0000 |
| commit | d668f69ee75f0dca73d625c21f860bffcc064182 (patch) | |
| tree | 4d44ded8bb054955188d43f1435be0f339db5789 /llvm/test/CodeGen/X86/required-vector-width.ll | |
| parent | 071699bf8280f077139e3b24633f4c140e961b78 (diff) | |
| download | bcm5719-llvm-d668f69ee75f0dca73d625c21f860bffcc064182.tar.gz bcm5719-llvm-d668f69ee75f0dca73d625c21f860bffcc064182.zip | |
Improve Dependency analysis when doing multi-node Instruction Selection
Relanding after fixing NodeId Invariant.
Cleanup cycle/validity checks in ISel (IsLegalToFold,
HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now do a full
search for cycles / dependencies pruning the search when topological
property of NodeId allows.
As part of this propogate the NodeId-based cutoffs to narrow
hasPreprocessorHelper searches.
Reviewers: craig.topper, bogner
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D41293
llvm-svn: 327171
Diffstat (limited to 'llvm/test/CodeGen/X86/required-vector-width.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/required-vector-width.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/required-vector-width.ll b/llvm/test/CodeGen/X86/required-vector-width.ll index 257d3f0d079..dcca540b31d 100644 --- a/llvm/test/CodeGen/X86/required-vector-width.ll +++ b/llvm/test/CodeGen/X86/required-vector-width.ll @@ -39,12 +39,12 @@ define void @add512(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "required-ve define void @avg_v64i8_256(<64 x i8>* %a, <64 x i8>* %b) "required-vector-width"="256" { ; CHECK-LABEL: avg_v64i8_256: ; CHECK: # %bb.0: -; CHECK-NEXT: vmovdqa 32(%rdi), %ymm0 -; CHECK-NEXT: vmovdqa (%rsi), %ymm1 -; CHECK-NEXT: vpavgb (%rdi), %ymm1, %ymm1 -; CHECK-NEXT: vpavgb 32(%rsi), %ymm0, %ymm0 -; CHECK-NEXT: vmovdqu %ymm0, (%rax) +; CHECK-NEXT: vmovdqa (%rsi), %ymm0 +; CHECK-NEXT: vmovdqa 32(%rsi), %ymm1 +; CHECK-NEXT: vpavgb (%rdi), %ymm0, %ymm0 +; CHECK-NEXT: vpavgb 32(%rdi), %ymm1, %ymm1 ; CHECK-NEXT: vmovdqu %ymm1, (%rax) +; CHECK-NEXT: vmovdqu %ymm0, (%rax) ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %1 = load <64 x i8>, <64 x i8>* %a |
