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authorSanjay Patel <spatel@rotateright.com>2015-05-22 21:10:06 +0000
committerSanjay Patel <spatel@rotateright.com>2015-05-22 21:10:06 +0000
commitba2ba80302182bcf1773c560b592949cd9a1d501 (patch)
tree925620c95192cb142122963aa9512b1676a00243 /llvm/test/CodeGen/X86/recip-fastmath.ll
parentb2f6afb30ac3285f2d2db310ed283398860f12fc (diff)
downloadbcm5719-llvm-ba2ba80302182bcf1773c560b592949cd9a1d501.tar.gz
bcm5719-llvm-ba2ba80302182bcf1773c560b592949cd9a1d501.zip
make reciprocal estimate code generation more flexible by adding command-line options
This patch adds a class for processing many recip codegen possibilities. The TargetRecip class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238051
Diffstat (limited to 'llvm/test/CodeGen/X86/recip-fastmath.ll')
-rw-r--r--llvm/test/CodeGen/X86/recip-fastmath.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/recip-fastmath.ll b/llvm/test/CodeGen/X86/recip-fastmath.ll
index fcd077092da..7f1521a83bc 100644
--- a/llvm/test/CodeGen/X86/recip-fastmath.ll
+++ b/llvm/test/CodeGen/X86/recip-fastmath.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx,use-recip-est | FileCheck %s --check-prefix=RECIP
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx,use-recip-est -x86-recip-refinement-steps=2 | FileCheck %s --check-prefix=REFINE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx -recip=divf,vec-divf | FileCheck %s --check-prefix=RECIP
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx -recip=divf:2,vec-divf:2 | FileCheck %s --check-prefix=REFINE
; If the target's divss/divps instructions are substantially
; slower than rcpss/rcpps with a Newton-Raphson refinement,
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