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| author | Dan Gohman <gohman@apple.com> | 2010-06-03 20:21:33 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-06-03 20:21:33 +0000 |
| commit | d83e3e7750f29c1e2dde2d1e48c2d74861cd3cd6 (patch) | |
| tree | 2edafff0f4cd5d289afffbc9d5188d845f554f2a /llvm/test/CodeGen/X86/promote-assert-zext.ll | |
| parent | cce5b81ce157a032c8ac7ffcefc0c1ea9871c814 (diff) | |
| download | bcm5719-llvm-d83e3e7750f29c1e2dde2d1e48c2d74861cd3cd6.tar.gz bcm5719-llvm-d83e3e7750f29c1e2dde2d1e48c2d74861cd3cd6.zip | |
Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
needs to demand the high bits because it's asserting that they're zero.
llvm-svn: 105406
Diffstat (limited to 'llvm/test/CodeGen/X86/promote-assert-zext.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/promote-assert-zext.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/promote-assert-zext.ll b/llvm/test/CodeGen/X86/promote-assert-zext.ll new file mode 100644 index 00000000000..b582806c96a --- /dev/null +++ b/llvm/test/CodeGen/X86/promote-assert-zext.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s | FileCheck %s +; rdar://8051990 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11" + +; ISel doesn't yet know how to eliminate this extra zero-extend. But until +; it knows how to do so safely, it shouldn;t eliminate it. +; CHECK: movzbl (%rdi), %eax +; CHECK: movzwl %ax, %eax + +define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind { +entry: + %tmp14 = load i8* %tmp13, align 1 + %tmp17 = zext i8 %tmp14 to i16 + br label %bb341 + +bb341: + %tmp18 = add i16 %tmp17, -1 + %tmp23 = sext i16 %tmp18 to i64 + ret i64 %tmp23 +} |
