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| author | Hal Finkel <hfinkel@anl.gov> | 2016-03-31 20:39:41 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2016-03-31 20:39:41 +0000 |
| commit | fc35391f2b4c36ec1a35d6e464ad972cf7117cdb (patch) | |
| tree | 026da57fa59dce0a2c65203543f5e5c01e23d310 /llvm/test/CodeGen/X86/memset-nonzero.ll | |
| parent | 132cd621216b7b09a170b9f10aa7494a87ce82fc (diff) | |
| download | bcm5719-llvm-fc35391f2b4c36ec1a35d6e464ad972cf7117cdb.tar.gz bcm5719-llvm-fc35391f2b4c36ec1a35d6e464ad972cf7117cdb.zip | |
[PowerPC] Add a late MI-level pass for QPX load/splat simplification
Chapter 3 of the QPX manual states that, "Scalar floating-point load
instructions, defined in the Power ISA, cause a replication of the source data
across all elements of the target register." Thus, if we have a load followed
by a QPX splat (from the first lane), the splat is redundant. This adds a late
MI-level pass to remove the redundant splats in some of these cases
(specifically when both occur in the same basic block).
This optimization is scheduled just prior to post-RA scheduling. It can't happen
before anything that might replace the load with some already-computed quantity
(i.e. store-to-load forwarding).
llvm-svn: 265047
Diffstat (limited to 'llvm/test/CodeGen/X86/memset-nonzero.ll')
0 files changed, 0 insertions, 0 deletions
