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| author | Jatin Bhateja <jatin.bhateja@gmail.com> | 2017-09-15 05:29:51 +0000 |
|---|---|---|
| committer | Jatin Bhateja <jatin.bhateja@gmail.com> | 2017-09-15 05:29:51 +0000 |
| commit | 908c8b37c2be23f86fb6d13aeb59598e302eb5b3 (patch) | |
| tree | 838765764d3ba048149e4fd00cc1b2ad682788b8 /llvm/test/CodeGen/X86/lea-opt-cse2.ll | |
| parent | 3e45e1081968d924d2174b4d4686f9ab4dd0a19d (diff) | |
| download | bcm5719-llvm-908c8b37c2be23f86fb6d13aeb59598e302eb5b3.tar.gz bcm5719-llvm-908c8b37c2be23f86fb6d13aeb59598e302eb5b3.zip | |
[X86] PR32755 : Improvement in CodeGen instruction selection for LEAs.
Summary:
1/ Operand folding during complex pattern matching for LEAs has been
extended, such that it promotes Scale to accommodate similar operand
appearing in the DAG.
e.g.
T1 = A + B
T2 = T1 + 10
T3 = T2 + A
For above DAG rooted at T3, X86AddressMode will no look like
Base = B , Index = A , Scale = 2 , Disp = 10
2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs
so that if there is an opportunity then complex LEAs (having 3 operands)
could be factored out.
e.g.
leal 1(%rax,%rcx,1), %rdx
leal 1(%rax,%rcx,2), %rcx
will be factored as following
leal 1(%rax,%rcx,1), %rdx
leal (%rdx,%rcx) , %edx
3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops,
thus avoiding creation of any complex LEAs within a loop.
Reviewers: lsaba, RKSimon, craig.topper, qcolombet
Reviewed By: lsaba
Subscribers: spatel, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D35014
llvm-svn: 313343
Diffstat (limited to 'llvm/test/CodeGen/X86/lea-opt-cse2.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/lea-opt-cse2.ll | 42 |
1 files changed, 18 insertions, 24 deletions
diff --git a/llvm/test/CodeGen/X86/lea-opt-cse2.ll b/llvm/test/CodeGen/X86/lea-opt-cse2.ll index 573b93dde43..73aeea06e6a 100644 --- a/llvm/test/CodeGen/X86/lea-opt-cse2.ll +++ b/llvm/test/CodeGen/X86/lea-opt-cse2.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s -check-prefix=X64 -; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s -check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+slow-3ops-lea | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=i686-unknown -mattr=+slow-3ops-lea | FileCheck %s -check-prefix=X86 %struct.SA = type { i32 , i32 , i32 , i32 , i32}; @@ -10,47 +10,41 @@ define void @foo(%struct.SA* nocapture %ctx, i32 %n) local_unnamed_addr #0 { ; X64-NEXT: .p2align 4, 0x90 ; X64-NEXT: .LBB0_1: # %loop ; X64-NEXT: # =>This Inner Loop Header: Depth=1 -; X64-NEXT: movl (%rdi), %eax -; X64-NEXT: movl 16(%rdi), %ecx -; X64-NEXT: leal 1(%rax,%rcx), %edx -; X64-NEXT: movl %edx, 12(%rdi) +; X64-NEXT: movl 16(%rdi), %eax +; X64-NEXT: movl (%rdi), %ecx +; X64-NEXT: addl %eax, %ecx +; X64-NEXT: incl %ecx +; X64-NEXT: movl %ecx, 12(%rdi) ; X64-NEXT: decl %esi ; X64-NEXT: jne .LBB0_1 ; X64-NEXT: # BB#2: # %exit -; X64-NEXT: addl %ecx, %eax -; X64-NEXT: leal 1(%rcx,%rax), %eax -; X64-NEXT: movl %eax, 16(%rdi) +; X64-NEXT: addl %eax, %ecx +; X64-NEXT: movl %ecx, 16(%rdi) ; X64-NEXT: retq ; ; X86-LABEL: foo: ; X86: # BB#0: # %entry -; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi ; X86-NEXT: .Lcfi0: ; X86-NEXT: .cfi_def_cfa_offset 8 -; X86-NEXT: pushl %esi ; X86-NEXT: .Lcfi1: -; X86-NEXT: .cfi_def_cfa_offset 12 -; X86-NEXT: .Lcfi2: -; X86-NEXT: .cfi_offset %esi, -12 -; X86-NEXT: .Lcfi3: -; X86-NEXT: .cfi_offset %edi, -8 +; X86-NEXT: .cfi_offset %esi, -8 ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .LBB0_1: # %loop ; X86-NEXT: # =>This Inner Loop Header: Depth=1 -; X86-NEXT: movl (%eax), %edx -; X86-NEXT: movl 16(%eax), %esi -; X86-NEXT: leal 1(%edx,%esi), %edi -; X86-NEXT: movl %edi, 12(%eax) +; X86-NEXT: movl 16(%eax), %edx +; X86-NEXT: movl (%eax), %esi +; X86-NEXT: addl %edx, %esi +; X86-NEXT: incl %esi +; X86-NEXT: movl %esi, 12(%eax) ; X86-NEXT: decl %ecx ; X86-NEXT: jne .LBB0_1 ; X86-NEXT: # BB#2: # %exit -; X86-NEXT: addl %esi, %edx -; X86-NEXT: leal 1(%esi,%edx), %ecx -; X86-NEXT: movl %ecx, 16(%eax) +; X86-NEXT: addl %edx, %esi +; X86-NEXT: movl %esi, 16(%eax) ; X86-NEXT: popl %esi -; X86-NEXT: popl %edi ; X86-NEXT: retl entry: br label %loop |

