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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-13 16:39:29 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-13 16:39:29 +0000 |
| commit | b5aaa673c64ecb86095bf69581e62de781816108 (patch) | |
| tree | 1b46adc51619317d24fd9b160f3b25941074b3bf /llvm/test/CodeGen/X86/known-signbits-vector.ll | |
| parent | c56f5728ee3aeefda6c03f63593520fb7de45b27 (diff) | |
| download | bcm5719-llvm-b5aaa673c64ecb86095bf69581e62de781816108.tar.gz bcm5719-llvm-b5aaa673c64ecb86095bf69581e62de781816108.zip | |
[X86][SSE] Add SSE vector imm/var shift support to SimplifyDemandedVectorEltsForTargetNode
llvm-svn: 349057
Diffstat (limited to 'llvm/test/CodeGen/X86/known-signbits-vector.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/known-signbits-vector.ll | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/known-signbits-vector.ll b/llvm/test/CodeGen/X86/known-signbits-vector.ll index 716e1fe5254..06ad258b8a5 100644 --- a/llvm/test/CodeGen/X86/known-signbits-vector.ll +++ b/llvm/test/CodeGen/X86/known-signbits-vector.ll @@ -165,8 +165,6 @@ define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwin ; X32-NEXT: sarl $30, %ecx ; X32-NEXT: vmovd %eax, %xmm0 ; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0 -; X32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0 -; X32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0 ; X32-NEXT: vpsrlq $3, %xmm0, %xmm0 ; X32-NEXT: vmovd %xmm0, %eax ; X32-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0 @@ -178,12 +176,10 @@ define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwin ; X64-LABEL: signbits_ashr_insert_ashr_extract_sitofp: ; X64: # %bb.0: ; X64-NEXT: sarq $30, %rdi -; X64-NEXT: vmovq %rsi, %xmm0 -; X64-NEXT: vmovq %rdi, %xmm1 -; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; X64-NEXT: vmovq %rdi, %xmm0 ; X64-NEXT: vpsrlq $3, %xmm0, %xmm0 ; X64-NEXT: vmovq %xmm0, %rax -; X64-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm0 +; X64-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0 ; X64-NEXT: retq %1 = ashr i64 %a0, 30 %2 = insertelement <2 x i64> undef, i64 %1, i32 0 |
