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| author | Preston Gurd <preston.gurd@intel.com> | 2012-10-29 15:01:23 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2012-10-29 15:01:23 +0000 |
| commit | 52dacca9773bd0a7df02b005dc56cf4caca02323 (patch) | |
| tree | 22da77bd5aa95c156d3a9b6263d57e9340add125 /llvm/test/CodeGen/X86/inlineasm-sched-bug.ll | |
| parent | bbc661e572fdcd4fd8b3829308e0328ad69cedd4 (diff) | |
| download | bcm5719-llvm-52dacca9773bd0a7df02b005dc56cf4caca02323.tar.gz bcm5719-llvm-52dacca9773bd0a7df02b005dc56cf4caca02323.zip | |
This patch addresses a problem with the Post RA scheduler generating an
incorrect instruction sequence due to it not being aware that an
inline assembly instruction may reference memory.
This patch fixes the problem by causing the scheduler to always assume that any
inline assembly code instruction could access memory. This is necessary because
the internal representation of the inline instruction does not include
any information about memory accesses.
This should fix PR13504.
llvm-svn: 166929
Diffstat (limited to 'llvm/test/CodeGen/X86/inlineasm-sched-bug.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/inlineasm-sched-bug.ll | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/inlineasm-sched-bug.ll b/llvm/test/CodeGen/X86/inlineasm-sched-bug.ll new file mode 100644 index 00000000000..08de0c02d29 --- /dev/null +++ b/llvm/test/CodeGen/X86/inlineasm-sched-bug.ll @@ -0,0 +1,13 @@ +; PR13504 +; RUN: llc -march=x86 -mcpu=atom <%s | FileCheck %s +; CHECK: bsfl +; CHECK-NOT: movl + +define i32 @foo(i32 %treemap) nounwind uwtable { +entry: + %sub = sub i32 0, %treemap + %and = and i32 %treemap, %sub + %0 = tail call i32 asm "bsfl $1,$0\0A\09", "=r,rm,~{dirflag},~{fpsr},~{flags}"(i32 %and) nounwind + ret i32 %0 +} + |
