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| author | Eric Christopher <echristo@apple.com> | 2011-12-01 08:12:41 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2011-12-01 08:12:41 +0000 |
| commit | 9da7f305a47270e76ca2690f985a435197e6c0c9 (patch) | |
| tree | 955acd31a266b8c934d3487654008ed30d42f302 /llvm/test/CodeGen/X86/inline-asm-q-regs.ll | |
| parent | 3a15e14520adfdddbf6657f878fe4c49fba41956 (diff) | |
| download | bcm5719-llvm-9da7f305a47270e76ca2690f985a435197e6c0c9.tar.gz bcm5719-llvm-9da7f305a47270e76ca2690f985a435197e6c0c9.zip | |
For 64-bit the rest of the general regs are ok for the q constraint. Make
sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
Diffstat (limited to 'llvm/test/CodeGen/X86/inline-asm-q-regs.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/inline-asm-q-regs.ll | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/inline-asm-q-regs.ll b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll index 1c8e2f9eec8..617bd39f096 100644 --- a/llvm/test/CodeGen/X86/inline-asm-q-regs.ll +++ b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll @@ -20,3 +20,10 @@ define void @test3(double %tmp) nounwind { call void asm sideeffect "$0", "q"(double %tmp) nounwind ret void } + +; rdar://10392864 +define void @test4(i8 signext %val, i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d) nounwind { +entry: + %0 = tail call { i8, i8, i8, i8, i8 } asm "foo $1, $2, $3, $4, $1\0Axchgb ${0:b}, ${0:h}", "=q,={ax},={bx},={cx},={dx},0,1,2,3,4,~{dirflag},~{fpsr},~{flags}"(i8 %val, i8 %a, i8 %b, i8 %c, i8 %d) nounwind + ret void +} |
